01-02-2020 06:39 AM
Hello, I am having an issue with a design and checking implementation I have notice that, in netlist window, the width of signals is incorrect. In my design, I have some wires declared with a width of 13. All bits of this wires are used because the wires comes from ADC and go to my control.
wire signed [12:0] adc_ir, adc_is, adc_it, adc_idc, adc_ir_conv, adc_it_conv; /* 13 bits adc */
When I check the netlist, the width of this signals is different of the width declared.
Honestly, I'm not sure if this number that I see in the netlist is corresponding with the width of the bus, but I think I'm right, but I'm not sure. can anyone explain it me? Or how I have to read the netlist? Thanks!
01-02-2020 08:44 AM
01-03-2020 12:06 AM
Thanks for the answer, but design works fine and I'm sure signals uses at least 12 bits because this signals are sended to other device and I can see them. Maybe that is not the width of the signals?
01-03-2020 12:21 AM
01-03-2020 12:45 AM
By work, I mean the design is been tested in production, with no major bugs. Anyway, I think that I see is not that I think, because according the schematic of adc_it, only one bit goes to SENSE module? This module compute the average...
Maybe this net is splitted in several nets with different names? Thanks!
01-03-2020 02:38 AM
01-03-2020 02:50 AM
Can you show the exact line of my posts where I say "my design is not tested"? I'm telling you that the design works correctly, if the width in netlist is correct, or is that I understand, nothing will works. Anyway, thanks.
01-03-2020 02:51 AM - edited 01-03-2020 02:52 AM
I asked about testing in simulation
"By work, I mean the design is been tested in production"
01-03-2020 10:43 AM
Hi @pablo_trujillo ,
You can wor around the issue by applying DONT_TOUCH attribute on nets. For syntax please check page no.49 of below link:
01-07-2020 01:48 AM - edited 01-07-2020 01:49 AM
I used this instruction and now the signals has the correct size, but I don't understand how the module can compute the average with only one bit of this signal. I still working for understand that. Thanks!!!
01-22-2020 10:27 PM
Hi @pablo_trujillo ,
That i am too not sure as might be coming from sytnhesis itself. For proper analysis we will be needing the test case at our end.
Till then DONT_TOUCH is valid work around.