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Contributor
Contributor
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Registered: ‎10-28-2018

Increamental complie only for sub module , not for the whole chip

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I use the increamental compile only for usb module , not the whole chip because the usb timing is critical.

So I use the following tcl script in post tcl of design initialization

read_checkpoint -incremental /home/ittmp1/khyu/fpga/aab033_khyu/VU440_FPGA16_IOB_r286_dram_nc_slr/aab033/checkpoint_1.dcp -reuse_objects [get_cells u_coreb033/u_usbtop/* ]

 

khyu_0-1596949053658.png

It work first, but fail at rout design . I got the error message.

ERROR: [Vivado_Tcl 4-384] DRC checks failed. Netlist or placement errors exist in this design. Please correct these errors before proceeding.

I update the my script to

read_checkpoint -incremental /home/ittmp1/khyu/fpga/aab033_khyu/VU440_FPGA16_IOB_r286_dram_nc_slr/aab033/checkpoint_1.dcp

But I got the same error

 

How can I do if I only want to refer to sub module , not the whole chip in increamtal comipler?

 

Thank you

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Xilinx Employee
Xilinx Employee
147 Views
Registered: ‎01-30-2019

Hi @khyu 

You are using read_checkpoint in a pre-hook TCL before place_design, this is not a recommended method of using the incremental implementation in project mode.

Please see this link to know about how to use Incremental Implementation in Project Mode.

Once you set the Incremental Checkpoint by the method mentioned in the link simply select the design run in the vivado GUI, go to its properties and add 

-reuse_objects [get_cells <cell_name>] in more options, Shown in attached image. 

Capture.PNG

Once this is done confirm the same in runme.log whether read_checkpoint -incremental -reuse_objects [get-cells <>] ./.....dcp is ran after opt_design or not.

Please try this and let us know

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Xilinx Employee
Xilinx Employee
311 Views
Registered: ‎01-30-2019

Hi @khyu ,

For using the incremental on a sub-module of the design, the option -reuse_objects is the correct option. So you are using the tool correctly but since the design is failing during routing ( even when the whole design is being reused ) you should debug on the cause of the DRC failure and routing failure.

Can you show us the DRC error you are getting?  

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Contributor
Contributor
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Registered: ‎10-28-2018

Hi Surajc:

         Error message is 

         ERROR: [DRC NDRV-1] Driverless Nets: Undriven nets found. Running opt_design will clean up the undriven nets from your design. Please ensure that opt_design has been run on your design and check the remaining
nets for DONT_TOUCH properties. The undriven nets in your design are: Net u_gckrst/u_coreb033_1/pclk_nx_out2_ are undriven.

 

The message tell I have driverless nets. and must run opt_design before router.

But I enable the opt_design 

 

I check runme.log  command flow

Command: link_design -top aab033 -part xcvu440-flga2892-2-e
Command: read_checkpoint -incremental /home/ittmp1/khyu/fpga/aab033_khyu/VU440_FPGA16_IOB_r286_dram_nc_slr/aab033/checkpoint_1.dcp
Command: report_drc -file aab033_drc_opted.rpt -pb aab033_drc_opted.pb -rpx aab033_drc_opted.rpx
Command: place_design -directive ExtraPostPlacementOpt
Command: phys_opt_design -directive AlternateFlowWithRetiming
Command: route_design -directive Explore

 

There is no opt_design command when I use the tcl command to execute the readcheckpoint  command 

If I use normal incremental flow , opt_design is executed 

Command: link_design -top aab033 -part xcvu440-flga2892-2-e
Command: opt_design
Command: report_drc -file aab033_drc_opted.rpt -pb aab033_drc_opted.pb -rpx aab033_drc_opted.rpx
Command: read_checkpoint -incremental /home/ittmp1/khyu/fpga/aab033_khyu/VU440_FPGA16_IOB_r286_dram_nc_slr/aab033/checkpoint_1.dcp
Command: place_design -directive ExtraPostPlacementOpt
Command: phys_opt_design -directive AlternateFlowWithRetiming
Command: route_design -directive Explore
Command: report_drc -file aab033_drc_routed.rpt -pb aab033_drc_routed.pb -rpx aab033_drc_routed.rpx
Command: report_methodology -file aab033_methodology_drc_routed.rpt -pb aab033_methodology_drc_routed.pb -rpx aab033_methodology_drc_routed.rpx
Command: report_power -file aab033_power_routed.rpt -pb aab033_power_summary_routed.pb -rpx aab033_power_routed.rpx

 

 

 

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Xilinx Employee
Xilinx Employee
254 Views
Registered: ‎01-30-2019

Hi @khyu ,

Seems like after reading the reference DCP there are some nets in the design ( probably in the sub-module added as a reference for Incremental Compile ) which are not driven.

Can you make sure that opt_design is run before reading the Incremental Checkpoint for the Sub-module? and Let us know ( try working on post-synth dcp with the following flow -> link_design -> opt_design -> read_checkpoint -> place..... )

Once we resolve the driverless nets issue by adding opt_design inflow, then we can look why opt is not running.

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Contributor
Contributor
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Registered: ‎10-28-2018

Hi Surajc:

                   I find the read_checkpoint tcl command must be placed at the tcl.pre of place design , not at the tcl.post of design initialization.

ie . correct flow is

design initial

opt_design

read_checkpoint

place_design

 

khyu_0-1597035654225.png

 

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Highlighted
Xilinx Employee
Xilinx Employee
148 Views
Registered: ‎01-30-2019

Hi @khyu 

You are using read_checkpoint in a pre-hook TCL before place_design, this is not a recommended method of using the incremental implementation in project mode.

Please see this link to know about how to use Incremental Implementation in Project Mode.

Once you set the Incremental Checkpoint by the method mentioned in the link simply select the design run in the vivado GUI, go to its properties and add 

-reuse_objects [get_cells <cell_name>] in more options, Shown in attached image. 

Capture.PNG

Once this is done confirm the same in runme.log whether read_checkpoint -incremental -reuse_objects [get-cells <>] ./.....dcp is ran after opt_design or not.

Please try this and let us know

View solution in original post