Infinite time for implementation

[colombini_luca]

Hi,

  I have got a design which keep routing forever.

 I attach a zip file containing the design, so that someone can try to replicate the issue.

  The design is basically an example design for 1G/10G/25G switching ethernet subsytem IP.

  Only pin constraints have been changed to adapt it to target ZCU102 board.

  I am using Vivado 2018.2.

Luca

[syedz]

@colombini_luca

The project which you shared has missing files. Can you share the archive project?

From Vivado GUI, select File-->Project-->Archive..  This will save your project in .zip file. Share this file. 

Did you try running different implementation strategies? Also try disabling multithreading: 

https://www.xilinx.com/support/answers/50345.html

Which OS are you using? Make sure you use supported OS with Vivado 2018.2: 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug973-vivado-release-notes-install-license.pdf#page=11

--Syed

[colombini_luca]

Hi @syedz,

  I cannot attach the archive since it is 25MB, even if I strip out the three include option.

  I am working on a Windows 10 64-bit machine.

Luca

[syedz]

@colombini_luca

I have sent you an email from ezmove where you can upload the file and send it back to us.

--Syed

[syedz · Accepted solution]

@colombini_luca

Thanks for the files. I checked this is in same vivado version i.e 2018.2 and the implementation took ~2hrs to complete. From log file, I see the tool took more time to fix hold violation which could not be closed. 

You need to review your constraints in the design. 

--Syed

[colombini_luca]

Thanks Syed