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02-07-2019 07:29 AM
Hi,
I have got a design which keep routing forever.
I attach a zip file containing the design, so that someone can try to replicate the issue.
The design is basically an example design for 1G/10G/25G switching ethernet subsytem IP.
Only pin constraints have been changed to adapt it to target ZCU102 board.
I am using Vivado 2018.2.
Luca
02-10-2019 08:51 PM
Thanks for the files. I checked this is in same vivado version i.e 2018.2 and the implementation took ~2hrs to complete. From log file, I see the tool took more time to fix hold violation which could not be closed.
You need to review your constraints in the design.
--Syed
02-07-2019 07:49 AM - edited 02-07-2019 07:50 AM
The project which you shared has missing files. Can you share the archive project?
From Vivado GUI, select File-->Project-->Archive.. This will save your project in .zip file. Share this file.
Did you try running different implementation strategies? Also try disabling multithreading:
https://www.xilinx.com/support/answers/50345.html
Which OS are you using? Make sure you use supported OS with Vivado 2018.2:
--Syed
02-07-2019 08:01 AM
Hi @syedz,
I cannot attach the archive since it is 25MB, even if I strip out the three include option.
I am working on a Windows 10 64-bit machine.
Luca
02-07-2019 08:52 AM
I have sent you an email from ezmove where you can upload the file and send it back to us.
--Syed
02-10-2019 08:51 PM
Thanks for the files. I checked this is in same vivado version i.e 2018.2 and the implementation took ~2hrs to complete. From log file, I see the tool took more time to fix hold violation which could not be closed.
You need to review your constraints in the design.
--Syed
02-10-2019 11:46 PM