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Visitor
Visitor
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Registered: ‎03-18-2020

Information of Shape Restriction or Placer Macro

Hi all,

    Recently, I am trying to place a design manually on Ultrascale device. However, I am confused by some placement failure caused by shape restriction but I failed to find any information about shape restriction in manuals.

    For example, when I try to place a LUTRAM (RAM32X1D), highlighted in white, to a new position like the figure shown below, I got the following error, indicating that the white LUTRAM has shape restriction with the red LUTRAM, but I cannot find where this restriction was defined. TAT

    ERROR: [Vivado 12-1409] Cannot set loc and bel property of instance(s) Bel does not match with the valid locations at which this instance can be placed. This instance is associated with a shape which contains instance design_1_i/xilinx_dma_pcie_ep_0/inst/xdma_0_i/inst/udma_wrapper/dma_top/dma_enable.vul_dma/RD/gen_rdwr_loop[0].gen_rdwr_eng.RDWR_INST/rcp_rcv_amt_101_reg_0_31_0_0/DP which has the following allowed location(s): G6LUT . The Bel mismatch is likely caused by this shape restriction.

    By digging into the problem, I noticed that Vivado defined some placer macro just like an example message shown below and I guess this cause shape restriction.

WARNING: [Vivado 12-4778] Additional cells/terminals have been unplaced. The cell(s) specified by unplace_cell belong to a placer macro, so the entire macro must be unplaced to maintain relative placement requirements. The unplaced cells/terminals are:
design_1_i/xilinx_dma_pcie_ep_0/inst/xdma_0_i/inst/udma_wrapper/dma_top/dma_enable.vul_dma/RD/gen_rdwr_loop[0].gen_rdwr_eng.RDWR_INST/rcp_rcv_amt_101_reg_0_31_6_6/DP
design_1_i/xilinx_dma_pcie_ep_0/inst/xdma_0_i/inst/udma_wrapper/dma_top/dma_enable.vul_dma/RD/gen_rdwr_loop[0].gen_rdwr_eng.RDWR_INST/rcp_rcv_amt_101_reg_0_31_6_6/SP
design_1_i/xilinx_dma_pcie_ep_0/inst/xdma_0_i/inst/udma_wrapper/dma_top/dma_enable.vul_dma/RD/gen_rdwr_loop[0].gen_rdwr_eng.RDWR_INST/rcp_rcv_amt_101_reg_0_31_4_4/DP
design_1_i/xilinx_dma_pcie_ep_0/inst/xdma_0_i/inst/udma_wrapper/dma_top/dma_enable.vul_dma/RD/gen_rdwr_loop[0].gen_rdwr_eng.RDWR_INST/rcp_rcv_amt_101_reg_0_31_4_4/SP
....................     ....................     ....................     ....................     ....................     ....................     ....................     

    Therefore, I wonder whether there is any available information about this kind of issue? THANKS IN ADVANCED!!!! ^_^/

shaperestriction.png

 

Best regards,

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-30-2019

Hi @zslwhkyuan 

See the solution of this post, marcb has defined the shapes in Vivado. Since these shapes are used internally by the tool, the user does not have to worry about it unless he/she runs into an error as you did.

In your design, can you check if the white and red LUTRAM's are related ( connected ) to each other ? which might be causing the tool to think them as a grouped logic and move them in a group instead of individual (  like what you are trying ) 

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Visitor
Visitor
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Registered: ‎03-18-2020

Hi @surajc ,

    THANKS A LOT for your prompt reply!

    Yes, the red and white LUTRAM share write address signals and I understand that a HLUT RAM is needed to provide write address signals to the rest of the RAM.

    I am using RapidWright, the Xilinx open-source tool, to try to do some placement for research and therefore, I wonder whether I can obtain the information that Vivado group some cells into a macro.

    Thanks again! ^_^/

Best regards,

   

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