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fpgalearner
Voyager
Voyager
5,603 Views
Registered: ‎04-11-2016

Initialize 2 D array VHDL

Hi,

Is the initlazation correct?

type x1 is std_logic_vector(15 downto 0);
type x2 (1 downto 0) of x1;
signal Y :  x2:=((others=>'0'), (others=>'0')); 

 

is initilization is also same for this?

 

type slv16_array_t is array (integer range <>) of std_logic_vector(15 downto 0);
signal Y : slv16_array_t(1 downto 0):=((others=>'0'), (others=>'0')); 

 

or something else?

 

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prathikm
Moderator
Moderator
5,574 Views
Registered: ‎09-15-2016

Hi @fpgalearner,

 

Can you try something like this?

 

subtype x1 is std_logic_vector(15 downto 0);
type x2 is array (1 downto 0) of x1 ;
signal Y : x2:=((others=> (others=>'0')));

 

Thanks & Regards,
Prathik
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fpgalearner
Voyager
Voyager
5,566 Views
Registered: ‎04-11-2016

hi @prathikm

I need actually for this case. Is this correct then?

type slv16_array_t is array (integer range <>) of std_logic_vector(15 downto 0);
signal Y : slv16_array_t(1 downto 0):=((others=> (others=>'0')));

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prathikm
Moderator
Moderator
5,522 Views
Registered: ‎09-15-2016

Hi @fpgalearner,

 

I guess this would work. But I am a bit confused about your usage. Do you have any RTL/test-case that you are working on?

type slv16_array_t is array (integer range <>) of std_logic_vector(15 downto 0);
signal Z : slv16_array_t(1 downto 0):=((others=> (others=>'0')));

 

Thanks & Regards,
Prathik
-----------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
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