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guruprasad_rt
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Registered: ‎02-17-2016

Instantiation of ODDR2

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Hi,

 

I went through the previous threads for this error, but couldnt get my problem solved. I am already usingODDR2 instance in my diesign to send the clock out(ODDR2 -> OBUF), this is working fine. But when I'm using ODDR2 as a flip-flop for the output pin(ODDR2 -> OBUF), I'm gitting this error(Did this change to get the better timing, as constraining and Plan ahead tools did not give the desired result, thought of placing this flop close to the PAD).

 

//Error Messange

 

ERROR:Pack:2531 - The dual data rate register
"i_spi_i2c_top/i_spi_slave/i_spi_miso" failed to join the "OLOGIC2" component
as required. The output signal for register symbol
i_spi_i2c_top/i_spi_slave/i_spi_miso requires general routing to fabric, but
the register can only be routed to ILOGIC, IODELAY, and IOB.

 

//Instantiation

 

   ODDR2 i_spi_miso (
            .Q  (spi_miso_ibuf),
            .C0 (spi_clk),
            .C1 (1'b0),
            .CE (1'b1),
            .D0 (miso_comb),
            .D1 (1'b0),
            .R  (1'b0),
            .S  (1'b0)
            );
 

OBUF i_spi_miso (.I(spi_miso_ibuf), .O(spi_miso));

 

-Guru

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gszakacs
Instructor
Instructor
16,936 Views
Registered: ‎08-14-2007

I see you're trying to use an ODDR2 as a standard flip-flop rather than DDR.  While I doubt that's the real cause of your error, this should be unnecessary.  My guess is that you have feedback from spi_miso in the design somewhere, and if you don't instantiate an IOBUF rather than OBUF for the pad, the tools will try to use internal routing for the feedback.  The ODDR2 and the single-rate output flop of an IOB are the same piece of hardware, so you should only have to add an IOB = FORCE constraint to push the required flop into the IOB.  If the tools give you an error on that, it means you have some feedback from the output of the flop going back into the design.  Sometimes XST can take care of this sort of feedback by replicating the register, but it won't do that for an instantiated ODDR2 where it isn't obvious to the tools that you could have used a standard fabric flop for the same function.  Try something like:

 

(* IOB = "FORCE" *) reg spi_miso;

 

always @ (posedge spi_clk) spi_miso <= miso_comb;

-- Gabor

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nupurs
Moderator
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Registered: ‎06-24-2015

Hi @guruprasad_rt

 

The outputs of ODDR2 should go to the output PAD's through the OBUF, and the outputs of ODDR2 cannot be looped back into the FPGA's internal logic. Please check in case if you are looping back from ODDR2 ouputs which is causing the problem.

 

Also, I can see that you have given the same name to both ODDR2 and OBUF, can you try once and verify with different names?

 

 

Thanks,
Nupur
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guruprasad_rt
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Registered: ‎02-17-2016

Hi Nupur S

 

As you said, I am not looping back the signal back to design. 

 

'OBUF i_spi_miso (.I(spi_miso_ibuf), .O(spi_miso));' spi_miso is directly going as output

 

Those two instances are at different hierachies, so it shouldn't be  problem.

 

-Guru

 

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vemulad
Xilinx Employee
Xilinx Employee
9,290 Views
Registered: ‎09-20-2012

Hi @guruprasad_rt

 

Can you open technology schematic and check what the output pin of ODDR2 instance is driving? Attach a snapshot of same here.

 

If possible attach NGC and UCF files so that we can check the same.

 

Thanks,

Deepika.

Thanks,
Deepika.
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gszakacs
Instructor
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Registered: ‎08-14-2007

I see you're trying to use an ODDR2 as a standard flip-flop rather than DDR.  While I doubt that's the real cause of your error, this should be unnecessary.  My guess is that you have feedback from spi_miso in the design somewhere, and if you don't instantiate an IOBUF rather than OBUF for the pad, the tools will try to use internal routing for the feedback.  The ODDR2 and the single-rate output flop of an IOB are the same piece of hardware, so you should only have to add an IOB = FORCE constraint to push the required flop into the IOB.  If the tools give you an error on that, it means you have some feedback from the output of the flop going back into the design.  Sometimes XST can take care of this sort of feedback by replicating the register, but it won't do that for an instantiated ODDR2 where it isn't obvious to the tools that you could have used a standard fabric flop for the same function.  Try something like:

 

(* IOB = "FORCE" *) reg spi_miso;

 

always @ (posedge spi_clk) spi_miso <= miso_comb;

-- Gabor

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guruprasad_rt
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Registered: ‎02-17-2016

Thank you Gabor & Deepika for the reply.

 

Gabor, I checked the design again, there is not feed back of spi_miso back into the design.

 

When I revisited the error messae with the help of my colleague, it says register can only be routed to IODELAY ILOGIC & IOB, but my miso register is coming from a slice(SLICE_X33Y37). Is it the cause for the error? Is the right order for ODDR instantiation is (IODELAY->ODDR2->OBUF)??

 

The other ODDR2 used in the design, is getting the input from PLL.

 

"i_spi_i2c_top/i_spi_slave/i_spi_miso requires general routing to fabric, but
the register can only be routed to ILOGIC, IODELAY, and IOB"

 

    -------------------------------------------------  -------------------
    SLICE_X33Y37.AQ      Tcko                         0.198    i_spi_i2c_top/i_spi_slave/miso
                                                                                        i_spi_i2c_top/i_spi_slave/miso
    A16.O                           net (fanout=5)        3.655   i_spi_i2c_top/i_spi_slave/miso
    A16.PAD                      Tioop                        1.396   spi_miso
                                                                                        i_spi_miso
                                                                                        spi_miso
    -------------------------------------------------  ---------------------------
    Total                                                              5.249ns (1.594ns logic, 3.655ns route)
                                                                                         (30.4% logic, 69.6% route)

 

 

-Regards

Guru

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vemulad
Xilinx Employee
Xilinx Employee
9,213 Views
Registered: ‎09-20-2012

Hi @guruprasad_rt

 

The structure should look like ODDR2 --> IODELAY --> OBUF. Please correct this.

Thanks,
Deepika.
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guruprasad_rt
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Registered: ‎02-17-2016

Gabor & Deepika,

 

On inspecting the design further, found that at different hierarchy, the signal was going into the chipscope, when it is prevented from going to the chipscope the issue was resolved.

 

Thank you for your help.

 

Guru