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Explorer
Explorer
132 Views
Registered: ‎04-12-2012

Internal LVDS termination with bias

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Hello,

I'm working on a PCB with an AC coupled LVDS clock input to my FPGA.

The designer forgot to connect the DC bias and termination resistors.

Can this be done internally ?

What's the XDC syntax for the resistors ?

AC_LVDS.JPG
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1 Solution

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54 Views
Registered: ‎01-22-2015

Re: Internal LVDS termination with bias

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I am just finding that unlike 7-Series, UltraScale has DQS_BIAS (pg69, UG571), which provides a DC bias of VCCO/2 to both the P and N sides of the LVDS input buffer – but only for AC-coupled LVDS in HP banks (just what you need).

set_property DQS_BIAS TRUE [get_ports <port_name>]

According to Table 1-55 of UG571, DQS_BIAS and DIFF_TERM_ADV can both be used in HP banks.

set_property DIFF_TERM_ADV TERM_100 [get_ports <port_name>]

I find no warnings that DQS_BIAS and DIFF_TERM_ADV cannot be used together.  Table 1-56 in UG571 shows some restrictions when using DQS_BIAS and EQUALIZATION.

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4 Replies
100 Views
Registered: ‎01-22-2015

Re: Internal LVDS termination with bias

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@shaikon 

In 7-Series FPGAs, the LVDS standard is only available in HP I/O banks and requires VCCO=1.8V (UG471, ~pg91).  Although an internal 100-ohm termination can be activated for LVDS, there is no FPGA internal bias voltage (as shown in your sketch).  A method of creating the bias, VICM, for AC-coupled LVDS is shown by Figure 1-72 in UG471, which uses resistors external to the FPGA.

You might be able to use the 7-Series IO standard called DIFF_SSTL18_II_DCI to bias and receive your AC-coupled LVDS.  DIFF_SSTL18_II_DCI is available in HP I/O banks and is described nicely by Figure 1-60 in UG471, which shows that split-termination resistors internal to the FPGA can be activated to bias each LVDS line to VCCO/2.  On about pages 27-28 of UG471, DIFF_SSTL18_II_DCI and the split-termination resistors are further described.

From Table 13 in the Kintex-7 datasheet (DS182), the output specifications for LVDS are VOCM=1.000-1.425V and VODIFF=0.247-0.600V.   These specifications seem to fit nicely with the input specifications for DIFF_SSTL18_II from Table 11 of DS182: VICM=0.300-1.425V and VIDIFF=0.100V(min).

I havn’t used DIFF_SSTL18_II_DCI to receive LVDS signals – but if you're in a pinch – it may be worth considering and trying.

Mark

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Explorer
Explorer
89 Views
Registered: ‎04-12-2012

Re: Internal LVDS termination with bias

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I'm using a Kintex Ultrascale FPGA. Not 7 series...

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76 Views
Registered: ‎01-22-2015

Re: Internal LVDS termination with bias

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Things seem pretty much the same for 7-Series and Ultrascale.  -see Fig 1-68 in UG571 and Tables 13 and 19 in DS892.

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55 Views
Registered: ‎01-22-2015

Re: Internal LVDS termination with bias

Jump to solution

I am just finding that unlike 7-Series, UltraScale has DQS_BIAS (pg69, UG571), which provides a DC bias of VCCO/2 to both the P and N sides of the LVDS input buffer – but only for AC-coupled LVDS in HP banks (just what you need).

set_property DQS_BIAS TRUE [get_ports <port_name>]

According to Table 1-55 of UG571, DQS_BIAS and DIFF_TERM_ADV can both be used in HP banks.

set_property DIFF_TERM_ADV TERM_100 [get_ports <port_name>]

I find no warnings that DQS_BIAS and DIFF_TERM_ADV cannot be used together.  Table 1-56 in UG571 shows some restrictions when using DQS_BIAS and EQUALIZATION.

Tags (1)