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fpgalearner
Voyager
Voyager
998 Views
Registered: ‎04-11-2016

Is DONT_TOUCH and compile Strategy don't fit together?

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Hi,

If I use (* DONT_TOUCH = "yes" *) during submodule instantiation, the synthesis strategy used in opt , P&R of vivado will not have any impact on this particular submodule?

I have timing issue now in a design which I am trying to solve with different strategies but unfortunately those timing violation is in that submodule where (* DONT_TOUCH = "yes" *) is used.

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fpgalearner
Voyager
Voyager
612 Views
Registered: ‎04-11-2016

The problem was in the synthesis which left a port in the top module unconnected.

View solution in original post

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rshekhaw
Xilinx Employee
Xilinx Employee
982 Views
Registered: ‎05-22-2018

Hi @fpgalearner ,

If we apply DONT_TOUCH in a design then Vivado Design Suite respects the DONT_TOUCH property during physical and logicL optimization. It does not perform physical or logical optimization on nets or cells with these properties.

Try running below command on post opt design and check guidelines on DONT_TOUCH:

xilinx::designutils::report_failfast

Thanks,

Raj.

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dpaul24
Scholar
Scholar
976 Views
Registered: ‎08-07-2014

@fpgalearner,

I have timing issue now in a design which I am trying to solve with different strategies but unfortunately those timing violation is in that submodule where (* DONT_TOUCH = "yes" *) is used.

It is a sub-module, right? What is exactly the timing issue?

In many cases for sub-modules, timing problems can be solved by just pipelining the internal sub-module design.

Well your case can be different. This is just an educated guess.

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fpgalearner
Voyager
Voyager
959 Views
Registered: ‎04-11-2016

@rshekhaw  I tried that command on post_route.dcp file of the design and comes:

xilinx::designutils::report_failfast
 -I- design metrics completed in 11 seconds
 -I- DONT_TOUCH metric completed in 3 seconds
 -I- utilization metrics completed in 103 seconds
 -I- control set metrics completed in 4 seconds
 -I- methodology check metrics completed in 60 seconds
 -I- average fanout metrics completed in 25 seconds (2 modules)
 -I- non-FD high fanout nets completed in 22 seconds
 -I- path budgeting metrics completed in 34 seconds
#  +-----------------------------------------------------------------------------------------+
#  | Design Summary                                                                          |
#  | checkpoint_fpga                                                                      |
#  | xcvu440-flga2892-1-c                                                                    |
#  +-----------------------------------------------------------+-----------+--------+--------+
#  | Criteria                                                  | Guideline | Actual | Status |
#  +-----------------------------------------------------------+-----------+--------+--------+
#  | LUT                                                       | 70%       | 18.00% | OK     |
#  | FD                                                        | 50%       | 4.95%  | OK     |
#  | LUTRAM+SRL                                                | 25%       | 0.07%  | OK     |
#  | CARRY8                                                    | 25%       | 1.97%  | OK     |
#  | MUXF7                                                     | 15%       | 1.16%  | OK     |
#  | DSP48                                                     | 80%       | 0.00%  | OK     |
#  | RAMB/FIFO                                                 | 80%       | 1.33%  | OK     |
#  | DSP48+RAMB+URAM (Avg)                                     | 70%       | 1.33%  | OK     |
#  | BUFGCE* + BUFGCTRL                                        | 24        | 7      | OK     |
#  | DONT_TOUCH (cells/nets)                                   | 0         | 34     | REVIEW |
#  | Control Sets                                              | 47493     | 7032   | OK     |
#  | Average Fanout for modules > 100k cells                   | 4         | 2.83   | OK     |
#  | Non-FD high fanout nets > 10k loads                       | 0         | 0      | OK     |
#  +-----------------------------------------------------------+-----------+--------+--------+
#  | TIMING-6 (No common primary clock between related clocks) | 0         | 6      | REVIEW |
#  | TIMING-7 (No common node between related clocks)          | 0         | 0      | OK     |
#  | TIMING-8 (No common period between related clocks)        | 0         | 0      | OK     |
#  | TIMING-14 (LUT on the clock tree)                         | 0         | 0      | OK     |
#  | TIMING-35 (No common node in paths with the same clock)   | 0         | 0      | OK     |
#  +-----------------------------------------------------------+-----------+--------+--------+
#  | Number of paths above max LUT budgeting (0.490ns)         | 0         | 132    | REVIEW |
#  | Number of paths above max Net budgeting (0.342ns)         | 0         | 120    | REVIEW |
#  +-----------------------------------------------------------+-----------+--------+--------+
 -I- Number of criteria to review: 4
 -I- This report should be run before placing the design and uses conservative guidelines beyond which runtime and timing closure will likely be more challenging
 -I- report_failfast completed in 262 seconds
xilinx::designutils::report_failfast: Time (s): cpu = 00:09:18 ; elapsed = 00:04:23 . Memory (MB): peak = 41185.027 ; gain = 2277.711 ; free physical = 127986 ; free virtual = 734656

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rshekhaw
Xilinx Employee
Xilinx Employee
949 Views
Registered: ‎05-22-2018

Hi @fpgalearner ,

If you see the DONT_TOUCH guidelines is 0 but in actual your design is having 34 so it is stating it should be reviewed.

Also will it be possible to share the post route dcp file with us?

Thanks,

Raj

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fpgalearner
Voyager
Voyager
909 Views
Registered: ‎04-11-2016

@rshekhaw 

xilinx::designutils::report_failfast -file failfast_postopt.rpt -detailed_reports postopt

As per here  https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1292-ultrafast-timing-closure-quick-reference.pdf

I run above command and see 34 cells which I put as DONT_TOUCH. What need to be reviewed here?

 

P.S. Unfortunately I can not share .dcp file.

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rshekhaw
Xilinx Employee
Xilinx Employee
885 Views
Registered: ‎05-22-2018

Hi @fpgalearner ,

You need to remove dont_touch if they are not critically required.

Thanks,

Raj

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hemangd
Moderator
Moderator
880 Views
Registered: ‎03-16-2017

@fpgalearner 

Kindly share your timing summary report (by running report_timing_summary -file <filepath>/test.txt ) after implementation completes. We will have to look into your timing reports to see what is causing timing violations. 

Regards,
hemangd

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fpgalearner
Voyager
Voyager
839 Views
Registered: ‎04-11-2016

@rshekhaw don't touch is critical. If I remove this, vivado trimmed it out during optimization. 

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marcb
Moderator
Moderator
800 Views
Registered: ‎05-08-2012

Hi @fpgalearner 

Without more information about the timing path in question, and the logic that has the DONT_TOUCH applied, it would be difficult/impossible for the community to help.

There should be a reason for the trimming (AR58616). Adjusting the design so that this logic is not trimmed would help remove the need for the DONT_TOUCH.

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rshekhaw
Xilinx Employee
Xilinx Employee
730 Views
Registered: ‎05-22-2018

Hi @fpgalearner ,

In that case as @hemangd and @marcb mentioned please share the timing summary report to further analyze the issue.

Thanks,

Raj

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fpgalearner
Voyager
Voyager
613 Views
Registered: ‎04-11-2016

The problem was in the synthesis which left a port in the top module unconnected.

View solution in original post

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