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Adventurer
Adventurer
9,092 Views
Registered: ‎10-21-2013

Is it possible to disable ILA (not delete) in Vivado?

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Is it possible to disable ILA (not delete) in Vivado, and than enable it again?

In ISE I can delete Chipscope definition file (.cdc) from project and then add the .cdc again.

 

Is this possible in Vivado?

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Xilinx Employee
Xilinx Employee
14,315 Views
Registered: ‎11-28-2007

Re: Is it possible to disable ILA (not delete) in Vivado?

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Hi Celeron,

 

assuming you are using Vivado 2014.1.

If you use the "normal" inserter flow, the information that was in the .CDC file in ISE, is now stored in the constraints XDC file that is set as "target".

You could move these debug constraints to a seperate XDC file and similarly to the IP, temporarily disable it, but not delete it or remove it from the project.

 

 

Best regards

Dries

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Xilinx Employee
Xilinx Employee
9,086 Views
Registered: ‎09-20-2012

Re: Is it possible to disable ILA (not delete) in Vivado?

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Hi,

 

If you are using Core generator flow, then select ILA IP and disable option "IS_ENABLED" in the properties tab. You also need to comment the ILA instantiation in the HDL.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
9,074 Views
Registered: ‎10-24-2013

Re: Is it possible to disable ILA (not delete) in Vivado?

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Hi, 

Here is the screenshot describing how to disable the file..

 

Thanks,Vijay
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Xilinx Employee
Xilinx Employee
14,316 Views
Registered: ‎11-28-2007

Re: Is it possible to disable ILA (not delete) in Vivado?

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Hi Celeron,

 

assuming you are using Vivado 2014.1.

If you use the "normal" inserter flow, the information that was in the .CDC file in ISE, is now stored in the constraints XDC file that is set as "target".

You could move these debug constraints to a seperate XDC file and similarly to the IP, temporarily disable it, but not delete it or remove it from the project.

 

 

Best regards

Dries

--------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if the information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.
Xilinx Employee
Xilinx Employee
9,020 Views
Registered: ‎10-24-2013

Re: Is it possible to disable ILA (not delete) in Vivado?

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Hi @celeron2000,
Did the above posts helped you finding the solution?
Please mark the post that helped you as a solution.
Thanks,Vijay
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Adventurer
Adventurer
8,996 Views
Registered: ‎10-21-2013

Re: Is it possible to disable ILA (not delete) in Vivado?

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Thank you. Just now I don't have any projects with ILA inserted, but I'll try Dries's suggestion. 

 

But it is a good idea to add the option "Disable/Enable ILA" in Vivado, isn't it? :)

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Scholar dwisehart
Scholar
8,959 Views
Registered: ‎06-23-2013

Re: Is it possible to disable ILA (not delete) in Vivado?

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I find that I want to edit the ILA probes as well as disable them and enable them.  While the GUI's are some help, I find that it is easy to accidentally do the wrong thing: like seting MARK_DEBUG to false when I really want to just delete the reference to the pin completely.  So instead I moved all of the ILA debug probes to a separate XDC file.  This way it is easy to enable and disable the whole file and by setting a few variables I can add or change probes easily.  Here is what is in my debug.xdc file:

 

set NAME ila1

create_debug_core $NAME ila
set CORE [get_debug_cores $NAME]

set_property ALL_PROBE_SAME_MU true $CORE
set_property ALL_PROBE_SAME_MU_CNT 4 $CORE
set_property C_ADV_TRIGGER true $CORE
set_property C_DATA_DEPTH 1024 $CORE
set_property C_EN_STRG_QUAL true $CORE
set_property C_INPUT_PIPE_STAGES 2 $CORE
set_property C_TRIGIN_EN false $CORE
set_property C_TRIGOUT_EN false $CORE

set_property port_width 1 [get_debug_ports $CORE/clk]

 

set BASE mFPGA/mTest

set CLK wTxUsrClk

set NET [get_nets $BASE/$CLK]
connect_debug_port $CORE/clk $NET

set CLK_NET [get_nets $NAME\_$CLK]

connect_debug_port dbg_hub/clk $CLK_NET

set DEBUG [get_debug_cores dbg_hub]
set_property C_CLK_INPUT_FREQ_HZ 322265625 $DEBUG
set_property C_ENABLE_CLK_DIVIDER true $DEBUG
set_property C_USER_SCAN_CHAIN 1 $DEBUG

 

set NETS [get_nets $BASE/txsequence[*]]
set WID 6
set PROBE $CORE/probe0
set_property MARK_DEBUG true $NETS
# create_debug_port $CORE probe   # First port is created by create_debug_core
set_property port_width $WID [get_debug_ports $PROBE]
connect_debug_port $PROBE $NETS

 

set NETS [get_nets $BASE/gt_txc[*]]
set WID 8
set PROBE $CORE/probe1
set_property MARK_DEBUG true $NETS
create_debug_port $CORE probe
set_property port_width $WID [get_debug_ports $PROBE]
connect_debug_port $PROBE $NETS

 

And so on.  By editing the highlighted values I quickly get the probes I want with an ability to enable and disable the whole XDC file.

 

Daniel