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mmatusov
Voyager
Voyager
964 Views
Registered: ‎02-17-2009

Is there a way in Vivado to add physical probe pins to an implemented design?

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This used to be possible in FPGA Editor. What is the best approach in Vivado?

 

Thanks,

/Mikhail

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hongh
Moderator
Moderator
1,069 Views
Registered: ‎11-04-2010
Hi, @mmatusov ,
You can try to use the command to modify the routed design directly.
Tools -> Xilinx tcl Store -> Debug Utilities (Install it and you can run the provided command xilinx::debugutils::add_probe )
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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hongh
Moderator
Moderator
1,070 Views
Registered: ‎11-04-2010
Hi, @mmatusov ,
You can try to use the command to modify the routed design directly.
Tools -> Xilinx tcl Store -> Debug Utilities (Install it and you can run the provided command xilinx::debugutils::add_probe )
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

mmatusov
Voyager
Voyager
956 Views
Registered: ‎02-17-2009

Thanks!

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