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580 Views
Registered: ‎10-08-2019

Is there any method to directly disable or downgrade the severity of RTSTAT DRCs?

Hi there,

I am working on Vivado. I am wondering if there is any possible way to disable the RTSTAT DRCs.

I know that these RTSTAT DRCs are related to some errors about routing (e.g. partially routed nets). Besides, they are read-only and will hinder the bitstream generation. 

Hope someone can tell me how to let Vivado ignore these checks. Thanks!

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7 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
529 Views
Registered: ‎05-22-2018

Hi zht247200@gmail.com ,

Yes you can disable them:

set_property IS_ENABLED 0 [get_drc_checks {<>}]

Check the below AR# link:

https://www.xilinx.com/support/answers/51543.html 

Thanks,

Raj 

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anunesgu
Moderator
Moderator
482 Views
Registered: ‎02-09-2017

Adding to @rshekhaw answer, you can also demote the error with the following command:

set_property SEVERITY {Warning} [get_drc_checks <>]

With the command above, you are able to downgrade an Error or Critical Warning to a "regular" Warning, which will allow you to proceed with bitstream generation.

The advantage is that the warning will still be there so you hopefully look at it in the future and fix it.

 

Andre Guerrero

Product Applications Engineer

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hongh
Moderator
Moderator
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Registered: ‎11-04-2010

Hi, zht247200@gmail.com ,

 I don't think RTSTAT related DRC can be disabled to generate bitstream.

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426 Views
Registered: ‎10-08-2019

Hi Raj,

Thanks for your reply.

set_property IS_ENABLED 0 [get_drc_checks {<>}]

 The method should be feasible for disabling those DRC rules which are not read-only. But as I said, the RTSTAT DRCs are read-only and thus cannot be disabled by such a tcl command. What I'm trying to do is to see if there is any possible way to disable those DRCs.

Thanks.

ZHT

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425 Views
Registered: ‎10-08-2019

Hi Andre,

Thanks for your reply.

As I said, the RTSTAT DRCs are read-only and thus cannot be downgraded by your command.

I have tried that way but it didn't work.

Thanks.

ZHT

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424 Views
Registered: ‎10-08-2019

Hi hongh,

Thanks for your reply.

You may be absolutely right. But I am trying to see if anyone knows some weird methods even bugs in Vivado to enable doing so.

Thanks

ZHT 

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rshekhaw
Xilinx Employee
Xilinx Employee
407 Views
Registered: ‎05-22-2018

Hi zht247200@gmail.com ,

Apologies my bad.

Then i guess the only way is to debug those partial route DRCs. Check the below AR# if that can help:

https://www.xilinx.com/support/answers/53854.html

Thanks,

Raj

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