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595 Views
Registered: ‎11-04-2016

Issue about IDELAY3 cascade

Hi All,

 

I've done a project which need using IDELAY3 cascade. I've checked the ug571-ultrascale-selectio spec(page 16) which introduce the cascade way of IDELAY3. But it comes out an error when implementation is doing which says 'Cannot set LOC property of ports, for bel IDELAY Could not route the logical net'. 

I use dqs clock which IOSTANDARD is LVCMOS18 and my FPGA is xcvu190-flgb2104-1-c-es2.

Thank you!

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2 Replies
565 Views
Registered: ‎11-04-2016

Re: Issue about IDELAY3 cascade

I‘ve fixed some connection issue for IDELAY cascade and run the implementation. There still one Critical warning says "Cannot set LOC property of ports, for bel IDELAY conflicting nets for physical connection OSERDES_OQ driven by BITSLICE_RX_TX_X0Y708.OSERDES.OQ: 1:my_nets_name;2: Ground(my_constraint LOC setting)"

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Moderator
Moderator
559 Views
Registered: ‎11-04-2010

Re: Issue about IDELAY3 cascade

Hi, @luciferlee024@gmail.com ,
The critical warning just mention you that the port whose IDELAYE3 is used cannot be set as a user port.
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