01-22-2018 07:06 PM
I've done a project which need using IDELAY3 cascade. I've checked the ug571-ultrascale-selectio spec(page 16) which introduce the cascade way of IDELAY3. But it comes out an error when implementation is doing which says 'Cannot set LOC property of ports, for bel IDELAY Could not route the logical net'.
I use dqs clock which IOSTANDARD is LVCMOS18 and my FPGA is xcvu190-flgb2104-1-c-es2.
01-23-2018 12:33 AM
I‘ve fixed some connection issue for IDELAY cascade and run the implementation. There still one Critical warning says "Cannot set LOC property of ports, for bel IDELAY conflicting nets for physical connection OSERDES_OQ driven by BITSLICE_RX_TX_X0Y708.OSERDES.OQ: 1:my_nets_name;2: Ground(my_constraint LOC setting)"
01-23-2018 01:19 AM