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Registered: ‎02-18-2019

JESD204 GLOBAL CLOCK (USING AS CORE CLOCK) ISSUE NOT GETTING IMPLEMENTED [Vivado 12-1411] Cannot set LOC property of ports

Sir, 

am usning zynq 7045 device to inteface my ADC (TI chip ads42jb69) 

adc Sampling rate  = 160Mhz  so lane rate is 1.6Gbps

Ref Clock Frequency  =  160Mhz

Core clock frequency =  40Mhz 

in "include shared logic in core mode" 

Ref clock is connected directly from GT Bank (MGTREFCLK0P_109_AD10 ) no error  

Global clock (core clock ) also am trying to connect from same bank MGTREFCLK1P_109_AF10 but it is giving so many errors

If I leave it open/tied to either 0 /1 also throwing error 

and also tried to with constraints like IS_LOC_FIXED and also create clock and other motheds but failed 

 

can anyone help me out how to connect the clock to Jesd or oany other Approrches need to be followed 

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance ADC1_JESD_CORE/inst/i_shared_clocks/i_glblclk_ibufds at AF10 (IPAD_X1Y10) since it belongs to a shape containing instance F_EXT1_CLK_REF_N. The shape requires relative placement between ADC1_JESD_CORE/inst/i_shared_clocks/i_glblclk_ibufds and F_EXT1_CLK_REF_N that can not be honoured because it would result in an invalid location for F_EXT1_CLK_REF_N. ["D:/Programs/Vivado/SPU240/SPU240.srcs/constrs_1/new/SPU.xdc":61]

corresponding error image attached here with 

please reply ASAP

thank you in advance 

 

 

 

dr ucio.JPG
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: JESD204 GLOBAL CLOCK (USING AS CORE CLOCK) ISSUE NOT GETTING IMPLEMENTED [Vivado 12-1411] Cannot set LOC property of ports

Hi balakrishnajatoth@gmail.com 

From an implementation (placement) standpoint, the message is indicating that the connectivity port -> buffer -> GT CHANNEL is all one relatively placed shape or macro. Vivado IPs will typically constrain the GT CHANNEL element. So if you have a port constraint that does not physically connect to the already constrained CHANNEL, then this would cause conflicting constraints, and the messaging you see.

Most IPs will allow you to adjust which GT Quad available within the customization GUI. That way the CHANNEL will be constrained the way you want, and a port constraint would not be needed.

If there are problems trying to change this in the JESD IP, the below Forums board might be a better spot for JESD specific questions.

https://forums.xilinx.com/t5/Xilinx-IP-Catalog/bd-p/OTHERIP

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Registered: ‎02-18-2019

Re: JESD204 GLOBAL CLOCK (USING AS CORE CLOCK) ISSUE NOT GETTING IMPLEMENTED [Vivado 12-1411] Cannot set LOC property of ports

Dear sir 

For my frequency requirements QPLL IS coming in the GUI

REF CLK IS 160MHZ

CORE CLK IS 40MHZ

PLEASE SUGGEST 

THANK YOU 

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Registered: ‎02-18-2019

Re: JESD204 GLOBAL CLOCK (USING AS CORE CLOCK) ISSUE NOT GETTING IMPLEMENTED [Vivado 12-1411] Cannot set LOC property of ports

Dear sir

Igonre previous post 

For my frequency requirements QPLL IS not coming in the GUI

REF CLK IS 160MHZ

CORE CLK IS 40MHZ

PLEASE SUGGEST 

THANK YOU

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Registered: ‎02-18-2019

Re: JESD204 GLOBAL CLOCK (USING AS CORE CLOCK) ISSUE NOT GETTING IMPLEMENTED [Vivado 12-1411] Cannot set LOC property of ports

please suggest Sirs
Ref clock is connected directly from GT Bank (MGTREFCLK0P_109_AD10 ) no error

Global clock (core clock ) also am trying to connect from same bank MGTREFCLK1P_109_AF10 but it is giving so many errors

If I leave it open/tied to either 0 /1 also throwing error

and also tried to with constraints like IS_LOC_FIXED and also create clock and other motheds but failed



can anyone help me out how to connect the clock to Jesd or oany other Approrches need to be followed

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance ADC1_JESD_CORE/inst/i_shared_clocks/i_glblclk_ibufds at AF10 (IPAD_X1Y10) since it belongs to a shape containing instance F_EXT1_CLK_REF_N. The shape requires relative placement between ADC1_JESD_CORE/inst/i_shared_clocks/i_glblclk_ibufds and F_EXT1_CLK_REF_N that can not be honoured because it would result in an invalid location for F_EXT1_CLK_REF_N. ["D:/Programs/Vivado/SPU240/SPU240.srcs/constrs_1/new/SPU.xdc":61]

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: JESD204 GLOBAL CLOCK (USING AS CORE CLOCK) ISSUE NOT GETTING IMPLEMENTED [Vivado 12-1411] Cannot set LOC property of ports

Hi balakrishnajatoth@gmail.com 

The earlier suggestion was to change the JESD IP customization to have the GTs placed where you want, and not constrain the GT REFCLK ports. Have you tried this?

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