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Visitor amirtofighiz
Visitor
506 Views
Registered: ‎12-19-2018

JESD204B TI Reference design Error building the design

Hi There,

I am trying to work with the JESD204B TI Reference design that can be found at,

http://www.ti.com/tool/tsw14j10evm

You can find it at the bottom of the page: TSW14J10EVM Xilinx Firmware Source (Rev. C) (it is also attached). 

I am using a TI ADC12J4000 through a TSW14J10 FMC board and connecting it to a KC705 Xilinx FPGA board.

Going through the PDF file attached, while running the command   "source ./script/build_it.tcl", I run into the following error:

[Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
synth_1
These failed run(s) need to be reset prior to launching 'impl_1' again.

I would appreciate it if somebody could help me understand what this error is.

Amir

P.S. I am attaching the log as well.

 

 

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Moderator
Moderator
364 Views
Registered: ‎01-16-2013

Re: JESD204B TI Reference design Error building the design

@amirtofighiz

 

Check the synthesis log file and see if there are any errors. From log file, I see the following message: 

ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
synth_1

 

How are you running the design in Vivado? Open the Vivado project using .xpr file and run synthesis and implementation.

 

--Syed

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