I am using KC 705 board to generate sequence from 4 GTX transceiver by using '7 Series FPGA TRanscxeiver Wizard' IP Core. I have customized it to default except that I am using gigabit ethernet protocal with 125 MHz of reference clock from G7 G8 FPGA U1 pins and 4 FMC-HPC transceiver.
I included the .xdc constraints file form the example project directory. But while synthesis it showed me an error that :
[Runs 36-252] 'Implementation' target generation is not supported for the IP ( gtwizard_v2_3_0.xci ). No files will be delivered for this target.
WARNING: [Runs 36-252] 'Implementation' target generation is not supported for the IP ( gtwizard_v2_3_0.xci ). No files will be delivered for this target.
In the synthesis and utilization report, it has not utilized any of the memory elements, then how will it be storing the .dat file data? It should have used some BRAM or ROM in order to store the data for transmitiing.
Also,it uses 545 IOBs whereas there are only 500 IOBs available on the board. So, in the implementation it gives an error about it. How to overcome this problem?
[Place 30-415] IO Placement failed due to overutilization. This design contains 545 I/O ports while the target device: 7k325t package: ffg900, contains only 500 available user I/O. The target device has 500 usable I/O pins of which 0 are already occupied by user-locked I/Os. To rectify this issue: 1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary. 2. Check the top-level ports of the design to ensure the correct number of ports are specified. 3. Consider design changes to reduce the number of I/Os necessary.