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Prasandh92
Adventurer
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Registered: ‎02-19-2021

LUT Combining in implementation

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Hi

Would like to understand why do I see the LUT combining during implementation as I am taking EDF netlist from Synplify and running place and route in Vivado 2020.2, want to know how it gets enabled?

-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 954 | 954 | 0 | 1 | 00:00:02 |

Note: Sorry the alignment is not proper

Is it possible to disable LUT combining during implementation

Thanks in advance

Prasanth S

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avrumw
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Registered: ‎01-23-2009

Before you go too deep into to looking for other sources of your congestion (like LUT combining), you need to look at your clocking.

The schematic you showed (which has a fabric net driving the clock pin of a clocked cell) is problematic. In an FPGA clock pins of clocked cells should (almost always) only be driven by dedicated clock networks (the output of BUFG/BUFH/BUFR/BUFIO). When driven from fabric logic (a locally routed clock) you will end up will very high clock skew, and will have large skew between gated clocks and ungated clocks on the same "domain". This skew will result in large hold time violations that the tools will attempt to fix using serpentine routing (using tons of routing resources to attempt to fix the hold times).

So it is highly likely that you congestion problem has nothing to do with LUT combining and everything to do with your clock structure.

Other than pure performance, probably the single biggest difference between ASIC and FPGA is how they deal with clocks. In an ASIC, the clock tree is built to suit the needs of the design - this means that clock multiplexers, clock gates, and other functional logic can be embedded within the clock trees; the ASIC clock insertion tool will accept these and balance the clock tree around them. In an FPGA, the clock tree is fixed - there is no possibility to embed functionality in the tree, and only limited capability at the clock root. This fundamental difference presents significant challenges to porting an ASIC (if it uses advanced clocking techniques) into an FPGA. 

Avrum

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syedz
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Registered: ‎01-16-2013

@Prasandh92 

 

LUT are combined to improve utilization during placer. It is on by default during PSIP (physical synthesis in placer). Any specific reason you would like to disable LUT combining?

Check topic "Disable LUT Combining" on page 271: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug949-vivado-design-methodology.pdf#page=271  

Also page 237 in UG912: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug912-vivado-properties.pdf#page=237  

 

If you would like to disable psip in placer then use "-no_psip" switch. Type "place_design -help" in vivado TCL to know more about switches in place_design. 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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hongh
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Registered: ‎11-04-2010

In which implementation stage do you see the info? 

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Prasandh92
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Thanks @syedz for the response,

The reason I want to disable LUT combining is due to routing congestion that I am facing during implementation, please take a look at the congested nets from the below attachment,

and also from the below schematic I am observing that the same LUT is trying to drive the clock pin of IDDRE1 and the data pin of FDRE,

Prasandh92_0-1625494289794.png

Thanks in advance,

Prasanth S,

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Prasandh92
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Registered: ‎02-19-2021

Thanks @hongh for the response,

I am seeing during place stage:

Phase 2.3.1 Physical Synthesis In Placer

 

Thanks in advance,

Prasanth S,

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syedz
Moderator
Moderator
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Registered: ‎01-16-2013

@Prasandh92 

 

Thanks. Check out the suggestions in my previous post to disable LUT combining. You can also try:

set_property HLUTNM DISABLED [get_cells <instance_name>]

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
hongh
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Registered: ‎11-04-2010

You can try -no_psip option for place_design.

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drjohnsmith
Teacher
Teacher
967 Views
Registered: ‎07-09-2009

The fact you have one net driving a clock input of a FF and a logic input, 

   is this what you are expecting, 

what circuit are you trying to make as this is a very in efficient method of coding,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Prasandh92
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Registered: ‎02-19-2021

Thanks @drjohnsmith for the response,

I am porting ASIC RTL into FPGA,

Whatever the scenario I am observing is possible to get implemented in ASIC?

Thanks in advance

Prasanth S

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drjohnsmith
Teacher
Teacher
820 Views
Registered: ‎07-09-2009

in an ASIC, the world is your oyster,

for instnace, ASICs us lots of gated clocks and lots of latches,

  neither of which are supported at all well by any FPGA,

  they have a global clock system and limited means to gate clocks, and the latches are not supported by the tools.

this lot might be of use about three films in the series, shows you the differences between asics and FPGAs

  although is heavily based upon putting existing ASIC code in FPGA.

https://www.youtube.com/watch?v=KNyQI3rXdp0&ab_channel=XilinxInc

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
How to create fast and efficient FPGA designs by leveraging your ASIC design experience. For more info visit: http://www.xilinx.com/training This course will...
avrumw
Expert
Expert
818 Views
Registered: ‎01-23-2009

Before you go too deep into to looking for other sources of your congestion (like LUT combining), you need to look at your clocking.

The schematic you showed (which has a fabric net driving the clock pin of a clocked cell) is problematic. In an FPGA clock pins of clocked cells should (almost always) only be driven by dedicated clock networks (the output of BUFG/BUFH/BUFR/BUFIO). When driven from fabric logic (a locally routed clock) you will end up will very high clock skew, and will have large skew between gated clocks and ungated clocks on the same "domain". This skew will result in large hold time violations that the tools will attempt to fix using serpentine routing (using tons of routing resources to attempt to fix the hold times).

So it is highly likely that you congestion problem has nothing to do with LUT combining and everything to do with your clock structure.

Other than pure performance, probably the single biggest difference between ASIC and FPGA is how they deal with clocks. In an ASIC, the clock tree is built to suit the needs of the design - this means that clock multiplexers, clock gates, and other functional logic can be embedded within the clock trees; the ASIC clock insertion tool will accept these and balance the clock tree around them. In an FPGA, the clock tree is fixed - there is no possibility to embed functionality in the tree, and only limited capability at the clock root. This fundamental difference presents significant challenges to porting an ASIC (if it uses advanced clocking techniques) into an FPGA. 

Avrum

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