03-18-2019 07:34 AM
I am using spartan6 to build a delay line consisting of some LUTs and CARRY4s.
I found a problem that the delay of each LUTs are not the same in the post P&R simulation, as maybe the addresses of input to these LUTs are not the same. For example, the first LUT use A2 as the input while the second LUT use A6.
I want the delay of each LUT to be same, but I do not know how to assign them all using the same address port like all A1 or all A2. Is there some way to do that?
03-18-2019 07:53 AM
It might help to know why you want the delays to be the same? What is the use case?
The next thing is that it might make sense to use a datapath delay constraint on those paths (Depending what you are trying to do)
The third is that the delays might be different, but since they change across PVT, you might not get the consistency in delays you want (Depending what you are trying to do)
Finally, you can use speedprint (https://www.xilinx.com/support/answers/6067.html) which will let you see what the delays are. So you can be sure what LUT delays are for your device, and then choose accordingly using the primitives and LOC constraints.
03-18-2019 08:01 AM
Thank you for your quick reply.
Actually I am building a Time to Converter based voltage sensor, which is sensitive to the change of delay caused by PTV factors. The number of LUTs could have impact on the sensitivity of the sensor, and I want to explore it. So I want each LUT as constant as possible.
I have already the placement constraint to assign each LUT to required LUT6 slices, but I could not assign the specific address A1-A6 of LUT6.
Do you have some ideas?
03-18-2019 08:13 AM
You should @ responses so users get the notifcation. Otherwise people don't know you responded.
It's been a while since I used ISE. You could do this in FED. Build your design, then manually unroute and place the pinouts of the LUTs and then assign them directly where you want them to go. But that is awaful. I wouldn't recommend it.
I might try using PlanAhead. I believe it gave you some more intutive control over placements in the device (But again it's been a while)
But it might make sense to use a Time Spec from to, with a max delay datapath only. If you set it strict enough that only one combination of paths will meet the requirment, the tool should choose those for you without needing to be more specific.
You might also want to share how you are instantiating your LUTs, and the speedprint is helpful to find the delays and see which ones actually match what you expect.
03-18-2019 01:11 PM
Thank you for your help!
Acually I could not do that in FPGA editor or Planahead even though I thought I could do. However, finally I found a way to keep the address assignment using "attribute S".
Now it looks all right in FPGA editor.