UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant yinglu2
Participant
207 Views
Registered: ‎06-24-2019

LUT cell generated in implementation

Hi,

I used a STARTUPE2 primitive in project. I opened the IMPLEMENTED DESIGN, why it generated STATRUPE2_inst_i_1 which is LUT cell (just as pic.1), while sometime, it just has only one cell (pic.2).Screen Shot 2019-09-04 at 1.35.16 PM.png

pic.1

Screen Shot 2019-09-04 at 1.35.07 PM.png

pic.2

Screen Shot 2019-09-04 at 1.35.16 PM.png

0 Kudos
3 Replies
Moderator
Moderator
199 Views
Registered: ‎01-16-2013

Re: LUT cell generated in implementation

@yinglu2 

 

Click on the STARTUPE2_inst_i_1(LUT5) cell and press F4 to see the schematic for its connections. I believe the implementation must be inserting the LUT cell during optimization. The information will be present in the log file. 

The pic2 without LUT5 must be from synthesized design.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Participant yinglu2
Participant
189 Views
Registered: ‎06-24-2019

Re: LUT cell generated in implementation

Thanks for your reply.

And the pic.2 is indeed opened in IMPLEMENTED DESIGN.

Screen Shot 2019-09-04 at 2.06.31 PM.png

0 Kudos
Moderator
Moderator
175 Views
Registered: ‎01-16-2013

Re: LUT cell generated in implementation

@yinglu2 

 

If pic2 is from implemented design then can you confirm pic1 is from synthesized design which has LUT5 cell?

Can you add -verbose switch under more options for opt_design and place_design in implementation settings as shown below. Rerun implementation and share the runme.log file which will be present in your project.runs folder:

Example <project>/<project>.runs/impl_1/runme.log file. 

image.png

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------