05-29-2013 09:05 AM
I was wondering if anybody could be so kind to explain a strange phenomenon to me. I used the UNISIM library to instantiate a 6-input lookup table as shown below:
LUT6_inst : LUT6 generic map ( INIT => X"0000000000000001" ) port map ( O => Output, I0 => Input0, I1 => Input1, I2 => Input2, I3 => Input3, I4 => Input4, I5 => Input5 );
If I open the placed and routed design in FPGA-editor, I can see an LUT6 clearly being instantiated. However, if I look at the value written to the FAR, a value of 0b00000000000100000000110000100100, and according to XAPP1088, bits 21:19 refers to the block type. These bits are "010" which indicates Block RAM content. How is this possible? Am I decoding the value written to FAR incorrectly or is this LUT actually mapped to BRAM?
05-29-2013 10:08 AM
What you see in FPGA Editor is an accurate representation of the implemented design. MAP would not put slice logic in a BRAM unless you are using the -bp switch and then only according to the rules specified here:
05-29-2013 12:26 PM - edited 05-29-2013 12:31 PM
Thanks for the reply. Unfortunately, I get a "502 bad gateway" when I click on the link (in fact, I am currently unable to access most Xilinx documentation on the support page). Anyhow, unless the -bp switch is enabled by default, I didn't enable it. I generated the bitrstream using FPGAeditor, if it makes a difference, but didn't specify any -bp switch. Are you suggesting that my decoding is erroneous?
Edit: I am able to access the Support site now, Might have been an internet issue,
05-29-2013 01:54 PM
Sorry, I don't know enough about the FAR decoding to comment on where you might be going wrong but if it doesn't agree with what you see in FPGA Editor then it erroneous.
05-31-2013 02:33 AM
Thanks again bwade. I think I might have determined the issue, but I am unable to explain it. Maybe you can assist.
I was investigating the FAR values of a partial reconfigurable design I implemented using difference-based reconfiguration ( the reason I generated the bitstream with FPGAeditor). In this bitstream I am quite certain the value decodes to a BRAM. However, if I go to the original bitsream, this value is nowhere to be found and the FAR value decodes correctly as an LUT. Is the difference-based bitstream still an accurate representation of a full bitstream, or is it possible that since it only reconfigures the differences between two designs, that it is not an accurate representation of a full bitstream? Could this cause a difference in the value written to FAR?