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Harish_Algat
Participant
Participant
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Registered: ‎06-04-2020

LUTs on the clock path due to latch clock gating

I have LUTs present on the clock path which is causing larger clock skew leading hold violations. The LUTs are there on the clock path due to Latch clock gating.

Is there any way to optimize that by using -gated_clock_conversion tool option?

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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

Not really

Much better to design your code to
a) get rid of latches
b) If you want to use gate clocking, use a bufgce
https://forums.xilinx.com/t5/Timing-Analysis/Right-way-to-clock-gate-with-BUFGCE/td-p/901082
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