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Adventurer
Adventurer
1,257 Views
Registered: ‎09-03-2015

LVDS P and N swapping in the FPGA

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Hello Guys,

 

i have the following problem:

I'm using 1G/2.5G Ethernet PCS/PMA or SGMII IP Core. RXN and RXP are connected to fix FPGA pins.

Unfortunatelly there is a mistake on the PCB layout. P and N are swapped.

So i have to swapp it again in the FPGA somehow. The Problm is, that the IP core doesn't allow me to connect RXN to a P pin.

After a look in the schematic, it generates the IBUFDS in the core

 

ip.PNG

 

So i cannot invert the Signals after the IBUFDS because it's protected in the ip core source.

I tried to instanciate an own IBUFDS bevore the SGMII IP core.

 

work_arround.PNG

But this work-around doesn't work because vivado complains about it:

 

error.PNG

 

Could you tell me why solution doesn't work?

And could you tell me what can i do otherwise?

Thank you very much.

 

best regards

 

Alex

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1 Solution

Accepted Solutions
Scholar jmcclusk
Scholar
1,573 Views
Registered: ‎02-24-2014

Re: LVDS P and N swapping in the FPGA

Jump to solution

It seems plausible that you can insert an inversion stage on gmii_rxd.    Is your TX interface also inverted?    Even if the IP is encrypted, you might still be able to modify the netlist using a TCL script.

Don't forget to close a thread when possible by accepting a post as a solution.
4 Replies
Scholar jmcclusk
Scholar
1,231 Views
Registered: ‎02-24-2014

Re: LVDS P and N swapping in the FPGA

Jump to solution

Flexibility at the IO interfaces is much more limited than in the fabric.  You'll probably have to invert the signal AFTER the IO cells, which means inverting 4 or 8 bits of data, after it's been deserialized.  

Don't forget to close a thread when possible by accepting a post as a solution.
Adventurer
Adventurer
1,187 Views
Registered: ‎09-03-2015

Re: LVDS P and N swapping in the FPGA

Jump to solution

thanks for your reply,

 

the problem is, that the sources of the IP Core are encrypted. So i cannot invert the signal after the io cells.

Does anyone has another idea, how to solve the problem?

What is with the Data channels from the IP?

ip_block.PNG

gmii_rxd and gmii_txd. Can i invert them? Does it make sence?

 

Thank you all

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Scholar jmcclusk
Scholar
1,574 Views
Registered: ‎02-24-2014

Re: LVDS P and N swapping in the FPGA

Jump to solution

It seems plausible that you can insert an inversion stage on gmii_rxd.    Is your TX interface also inverted?    Even if the IP is encrypted, you might still be able to modify the netlist using a TCL script.

Don't forget to close a thread when possible by accepting a post as a solution.
Adventurer
Adventurer
1,165 Views
Registered: ‎09-03-2015

Re: LVDS P and N swapping in the FPGA

Jump to solution

Yes, my TX interface is also inverted.

The idea with the TCL script sounds good. I will try it out, thanks.

Better solution for me would be to set it by a constraint.

 

Thanks

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