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Adventurer
Adventurer
261 Views
Registered: ‎05-18-2018

LVDS output differential voltage is too high

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I am using Vivado 2019.1 and am developing a project for the Zynq Ultrascale+.

In my Vivado project, I have pins driven by OBUFDS primitives that are set to LVDS. According to UG925, the differential mode output voltage should be ~350 mV, and the output common mode voltage should be about ~1.25 V.

Using a differential probe, I am seeing the following voltages. The differential mode voltage is ~700 mV.

video_clk.PNG

 

According to Vivado, the pins are set to LVDS mode:

flex_video_clk.PNG

lvds_spec.png

What am I doing wrong/misunderstanding?

 

Thanks.

lvds_spec.png
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1 Solution

Accepted Solutions
172 Views
Registered: ‎07-23-2019

Re: LVDS output differential voltage is too high

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@joelschad 

VODIFF is the voltage swing (in one line) between high and low, or, between + and - lines, as they will always be opposite.

When a differential signal is translated to single ended (i.e. subtracted), it produces a +/- VODIFF signal, so what you see on a scope with a differential probe (that translates from diff to single ended) is a jump of 2x VODIFF.

If you just probed a line, you will see the 350 - 400 mV swing.

6 Replies
236 Views
Registered: ‎06-21-2017

Re: LVDS output differential voltage is too high

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Are your signals terminated at the receiving side?

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Adventurer
Adventurer
234 Views
Registered: ‎05-18-2018

Re: LVDS output differential voltage is too high

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Yes, I have them set up with off-chip FD_100 termination in Vivado's Implementation flow, and I have 100Ω resistors across the pins on the breakout board I'm using to observe the signals.

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Scholar drjohnsmith
Scholar
208 Views
Registered: ‎07-09-2009

Re: LVDS output differential voltage is too high

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Do you have a differential buffer driving in your fpga.

One thought, and Im to tired to think this through, Appologies.
Is it the differential probe effect ?
As one side goes up 350 mV, the other goes down 350 mV,
so the probe sees that as 700 mV difference ?

Wonder what a single ended probe on one would show ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Adventurer
Adventurer
183 Views
Registered: ‎05-18-2018

Re: LVDS output differential voltage is too high

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I think you're right.

I went back and looked at a differential signal on a Zynq 7 design and saw the same 2x-my-expectation voltages. The DS925 description implies that the Q-Q' voltage is only 350 mV nominal, but, as you said, the voltage swing on each channel is 350 mV nominal, for total swing of 700 mV.

 

 

lvds_levels_ds925.png

This diagram shows the expected waveforms, and several app notes confirm this.

lvds_levels.png

 

173 Views
Registered: ‎07-23-2019

Re: LVDS output differential voltage is too high

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@joelschad 

VODIFF is the voltage swing (in one line) between high and low, or, between + and - lines, as they will always be opposite.

When a differential signal is translated to single ended (i.e. subtracted), it produces a +/- VODIFF signal, so what you see on a scope with a differential probe (that translates from diff to single ended) is a jump of 2x VODIFF.

If you just probed a line, you will see the 350 - 400 mV swing.

Highlighted
Explorer
Explorer
156 Views
Registered: ‎06-25-2014

Re: LVDS output differential voltage is too high

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And to just drive this home, the Xilinx datasheet is also telling you the same.

Where this snippet highlighted is the impotant bit. i.e.

Capture.PNG

Which is basically saying the 350mV figure is the abs value. So, using the numbers from that diagram you posted:

Capture2.PNG

when Q is high the figure is taken from Q - ~Q = 1.35-1.05 = 300mV, and when ~Q is high the number is again1.35 - 1.05 = 300mV

 

 

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