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sprl111
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Registered: ‎05-07-2012

[Labtools 27-1973] Mismatch between the design programmed into the device xc7k325t

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Hello,

 

I modified my ILA core and upon opening the Vivado Hardware Manager after a rebuild I got the error below.  I have no idea what this is telling me and I'm having difficulity understanding that Vivado can't handle the file management associated with the modification of a core followed by a rebuild.  Does anyone understand what this error is saying and why it is saying it?  What's an ltx file?  Thank you.

 

 [Labtools 27-1973] Mismatch between the design programmed into the device
 xc7a200t (JTAG device index = 0) and the probes file
 C:/GD/GEOSTAR_Demonstrator_Control.xpr/GEOSTAR_Demonstrator_Control/GEOSTAR_Dem
 onstrator_Control.runs/impl_3/debug_nets.ltx.
 
 The device core at location user chain=1 index=0, has 1 ILA Input port(s), but the core in the probes file has 2 ILA Input port(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file OR
2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.

 

 

 

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pratham
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Registered: ‎06-05-2013

@sprl111 right click on the FPGA in hardware manager and refresh the device. If you made some changes in the design i.le added ILA port then it has to generate new ltx file once you run the implementation.

-Pratham

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pratham
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@sprl111 .LTX file wil have the all the ILA debug infromation.

 

The error message is saying that device has one ILA port but the ltx file but core in the probes file has 2 ILA Input port(s).

 

Can you please refresh the device or power off-on the FPGA? once done open the hardware manager assign the newly created .bit file and check in the properties it will show which .ltx file it is going to used. You can also open the .ltx file and notepad editor anc check if the ltx has the newly added ILA ports by you.

-Pratham

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sprl111
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How does one refresh the device?  Where do I find a new ltx file?  I looked in the implementation folder and there is only one ltx file and that's the file that the Hardware Manager doesn't like. Why doesn't Vivado generate a new appropriate ltx file when it builds the bit file? 

 

Thanks.

 

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pratham
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Registered: ‎06-05-2013

@sprl111 right click on the FPGA in hardware manager and refresh the device. If you made some changes in the design i.le added ILA port then it has to generate new ltx file once you run the implementation.

-Pratham

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pratham
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@sprl111 Did that help?

-Pratham

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aher
Xilinx Employee
Xilinx Employee
10,320 Views
Registered: ‎07-21-2014
Hi,

Is the clock that you are using for ILA core meeting timing (after doing modifications)? this issue is also seen if clock domian that you are using is violating the timing and ILA core fails to respond even if you use correct .ltx file.

Thanks,
Shreyas
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sprl111
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Registered: ‎05-07-2012

Sorry,

 

Yes, that worked.

 

Thanks.

 

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sprl111
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Registered: ‎05-07-2012

I opened a webcase on it and I slowed the JTAG clock to its slowest setting.  The ILA is working now.

 

Thanks.

 

 

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527114591@qq.com
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Registered: ‎10-15-2019
What is webcase in vivado? Thanks
Fresh
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bklopp
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Registered: ‎05-16-2018

Vivado is basically unusable. I have been put behind by weeks from wrestling with this tool.

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