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orangelynx
Observer
Observer
17,328 Views
Registered: ‎09-22-2015

Leave top level ports unplaced

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Hi,

 

I have a block design which I use as an entity in my top level design and most ports of the block design are routed straight to top level ports.

 

However some ports I do not wish to use in my current debug implementation and therefore do not want to place these ports. This however prevents me from generating a bitstream because the DRC error is rated as an error.

 

I read in another thread that the ports would get trimmed if there are not constraints regarding these ports, but this seems not to be the case (could be possible thought that some IP of the block design has some constraint on the port - at least i removed all constraints I added manually)

 

Using the PROHIBIT constraint did not solve the issue either.

 

How can I tell Vivado to ignore / not place certain top level ports?

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vemulad
Xilinx Employee
Xilinx Employee
28,894 Views
Registered: ‎09-20-2012

Hi @orangelynx

 

If you want to downgrade the error you can follow the steps mentioned in AR http://www.xilinx.com/support/answers/56354.html

 

Even if you downgrade the Implementation tool will map the ports to some package pins. You can open Implemented design, change the layout to IO planning and check the IO ports window to find the package pins assigned by the tool. or you can check IO report in reports tab.

 

Thanks,

Deepika.

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
17,326 Views
Registered: ‎09-20-2012

Hi @orangelynx

 

If this is top level port and it is unconnected then the tool cannot trim it. During Implementation even if you dont assign LOC constraint the tool chooses some package pin for the top level port. If you want you can downgrade the DRC or modify the RTL to remove these unused top level ports.

 

This AR can be helpful http://www.xilinx.com/support/answers/56354.html

 

Thanks,

Deepika.

Thanks,
Deepika.
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syedz
Moderator
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Registered: ‎01-16-2013

@orangelynx,

 

Can you share the DRC error you are getting? As @vemulad pointed try to downgrade the Error using "set_msg_config" 

Check page number 1303 in below UG to know the syntax details:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug835-vivado-tcl-commands.pdf

 

--Syed

 

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orangelynx
Observer
Observer
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Registered: ‎09-22-2015

Hi,

 

the error is

 

[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 7 out of 225 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: TDD_SYNC, SPI_UDC_CSN_TX, SPI_UDC_CSN_RX, SPI_UDC_SCLK, SPI_UDC_DATA, GPIO_MUXOUT_TX, GPIO_MUXOUT_RX.

 

and

 

[DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 7 out of 225 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: TDD_SYNC, SPI_UDC_CSN_TX, SPI_UDC_CSN_RX, SPI_UDC_SCLK, SPI_UDC_DATA, GPIO_MUXOUT_TX, GPIO_MUXOUT_RX.

 

What will happen to the ports if I degrade the warning? Will Vivado leave them unconnected for sure? or auto map them to some other place?

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vemulad
Xilinx Employee
Xilinx Employee
28,895 Views
Registered: ‎09-20-2012

Hi @orangelynx

 

If you want to downgrade the error you can follow the steps mentioned in AR http://www.xilinx.com/support/answers/56354.html

 

Even if you downgrade the Implementation tool will map the ports to some package pins. You can open Implemented design, change the layout to IO planning and check the IO ports window to find the package pins assigned by the tool. or you can check IO report in reports tab.

 

Thanks,

Deepika.

Thanks,
Deepika.
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orangelynx
Observer
Observer
17,294 Views
Registered: ‎09-22-2015

so its no longer possible to leave them completely unmapped (as discussed here: https://forums.xilinx.com/t5/Welcome-Join/Correct-procedure-for-handling-unconnected-ports/td-p/385331) ? the only way is to modify the RTL?

 

bummer, it would be really useful for debugging.. 

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fransschreuder
Participant
Participant
15,093 Views
Registered: ‎08-12-2010

Yes, I would also like to have an option to remove toplevel ports. I am for instance using the same VHDL code on two different boards, on one board it needs some additional output pins that I don't want to use on the second board. It would be very useful to be able to disable them depending on some generics or constraints.

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mbruno222
Visitor
Visitor
11,033 Views
Registered: ‎10-03-2012

On my last design, done in Vivado 2015.1, I did exactly what fransschreuder said: I have one top level VHDL file that works on three different boards - a Xilinx eval board and two spins of our production board, none of which share exactly the same I/O. The ports that are not common are only connected inside GENERATE blocks that check which board it is being synthesized for.

 

This worked fine in Vivado 2015.1 - as long as the unused output ports were unconnected in the VHDL and had no constraints in the XDC file, the ports were trimmed away. Looking at the schematic view in the implemented design, I see only the ports with no logic attached. Bitstream generation runs without any errors.

 

I am now working on a new design using Vivado 2017.1 and am trying to use the same approach. Unfortunately I am running into the same problem discussed in this thread. Looking at the schematic view in the implemented design shows the unused output ports all connected to ground. Clearly this changed sometime between 2015.1 and 2017.1.

 

I am thinking about assigning the unused outputs to 'Z' and downgrading the error to a warning. That way it shouldn't matter to which random pins the ports get assigned. But it would be nice to be able to trim away the unused ports. This is something we've been able to do for a long time... it was defined behavior in ISE and it worked for a while in Vivado. Why has this changed?

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mbruno222
Visitor
Visitor
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Registered: ‎10-03-2012

I figured out how to leave top level ports unplaced (at least in Vivado 2017.1). I read through the synthesis attributes in the synthesis user guide (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug901-vivado-synthesis.pdf) and noticed the IO_BUFFER_TYPE attribute. I tried it out and it solves our problem.

 

You need to set the "IO_BUFFER_TYPE" attribute to "none" on the top level ports that you want unplaced. This can be done either in your HDL or XDC constraints file. I am doing it in my constraints file since each board has its own, whereas the top level VHDL file is shared.

 

In the XDC, for each unused port:

 

set_property IO_BUFFER_TYPE none [get_ports unused_port_name]

 

After applying this attribute to the unused ports and re-running synthesis and implementation, I can verify that in the schematic view of the implemented design that my unused top level ports are no longer connected to ground. Bitstream generation now runs without the rule violations.

 

I know this thread is a over a year old, but hopefully this solution helps others with the same issue who find this thread.

futureishere
Participant
Participant
8,264 Views
Registered: ‎12-04-2014

I am using Vivado 2017.4 and if I set the IO_BUFFER_TYPE to none for unconnected ports, I get the IO port is missing a buffer error in opt_design stage.

anand_1995
Visitor
Visitor
2,054 Views
Registered: ‎12-15-2019

Getting error while doing :

set_property IO_BUFFER_TYPE none [get_ports port_name] 

[DRC RPBF-1] IO port is missing a buffer: Device port BRAM_PORTA_0_din[0] should be connected to an IO cell such as an [IO]BUF*.

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