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Visitor ad@itdev
Visitor
258 Views
Registered: ‎09-24-2018

Lock net through BUFH (specify clock to a region)

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I have a design with lots of differnt clocks and am frequently having placer issues where 90% of my builds fail placement due to the clock placer failing as some regions have more than 12 clocks each (sometimes 13 or 14) this is on a kintex 7 device.

 

For my understanding BUFGs route though BUFHs into each region.

I would like to lock which clock nets travel through each BUFH in one or two regions to assist the placer.

I am unable to "FIX" the BUFH as they are not explictly used (the signal just routes through them) and I obviously don't want to lock the entire clock net.

Ideally I just want to specify what clocking nets enter a specific region or state which net/BUFG is sourced by a BUFH.

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1 Solution

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Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎05-08-2012

Re: Lock net through BUFH (specify clock to a region)

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Hi ad@itdev 

Do you see warnings or errors when overlapping pblocks? I thought this was acceptable if you are not in a hierarchical flow, and need to set the EXCLUDE_PLACEMENT or CONTAIN_ROUTING pblock properties.

Alternatively, you could try manually instantiating a BUFH and branching off of the BUFG on the logic you want within a specific clock region. The normal pblock should be an easier solution though.

There is also the option to  control the clock partitioning through explicit pblocks. The placer generates clock partitioning by setting an area where the loads can reside. The below AR shows how to manually adjust the partitioning.

https://www.xilinx.com/support/answers/66386.html


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3 Replies
Moderator
Moderator
255 Views
Registered: ‎11-04-2010

Re: Lock net through BUFH (specify clock to a region)

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Hi, ad@itdev ,

You can try to add floorplan constraint(Pblock) for the loads of the target clock and the pblock constians the specific clock regions.

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Visitor ad@itdev
Visitor
244 Views
Registered: ‎09-24-2018

Re: Lock net through BUFH (specify clock to a region)

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This may work in a couple of cases, so I will try it (thanks).

However it doesn't solve the general case as I am already using PBlocks to contrain some sections of logic, these are necessarily not always aligned to clock region boundaries.

Therefore in order to use PBlocks I would need to have overlapping blocks which is not allowed.

 

Representative Example:

For logic to place and route I need a PBlock to cover half of X1Y0 and all of X1Y1, X1Y2 - this cannot be changed or the design starts to fail routing here and elsewhere.

For clocks I want to constrain what enters X1Y0 as the tool tries to add 13 clocks, I cannot create a second PBlock in this case as it would overlap the first.

Ideally I am after something that is more of a LOC for my routing through the uninstantiated BUFH.

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Xilinx Employee
Xilinx Employee
225 Views
Registered: ‎05-08-2012

Re: Lock net through BUFH (specify clock to a region)

Jump to solution

Hi ad@itdev 

Do you see warnings or errors when overlapping pblocks? I thought this was acceptable if you are not in a hierarchical flow, and need to set the EXCLUDE_PLACEMENT or CONTAIN_ROUTING pblock properties.

Alternatively, you could try manually instantiating a BUFH and branching off of the BUFG on the logic you want within a specific clock region. The normal pblock should be an easier solution though.

There is also the option to  control the clock partitioning through explicit pblocks. The placer generates clock partitioning by setting an area where the loads can reside. The below AR shows how to manually adjust the partitioning.

https://www.xilinx.com/support/answers/66386.html


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
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