Logic Analyzer incompatible with other IP?

[geerard]

I'm using a Kintex-7 FPGA on a KC705 platform and using various IP cores from Xilinx:

- Clocking Wizard (5.2)

- 10G Ethernet PCS/PMA (10GBASE-R) 6.0

- FIFO Generator (13.0)

I would like to use the ILA (Integrated Logic Analyzer) (6.0), but get an error regarding the clock routing of the SI5326_OUT_C_N when I try to integrate this ILA into the system. Can someone explain why this happens and what I can do about it?

I get the following error:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SI5326_OUT_C_N_IBUF] >

    SI5326_OUT_C_N_IBUF_inst (IBUF.O) is locked to IPAD_X1Y45
     SI5326_OUT_C_N_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

    The above error could possibly be related to other connected instances. Following is a list of
    all the related clock rules and their respective instances.

    Clock Rule: rule_gt_bufg
    Status: PASS
    Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_i/U0/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i (GTXE2_CHANNEL.TXOUTCLK) is locked to GTXE2_CHANNEL_X0Y10
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_shared_clock_reset_block/txoutclk_bufg_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y28

    Clock Rule: rule_gt_bufhce
    Status: PASS
    Rule Description: A GT driving a BUFH must both be in the same horizontal row (clockregion-wise)
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_i/U0/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i (GTXE2_CHANNEL.RXOUTCLK) is locked to GTXE2_CHANNEL_X0Y10
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_0_local_clock_reset_block/rxoutclk_bufh_i (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X1Y71

    Clock Rule: rule_bufh_bufr_ramb
    Status: PASS
    Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
    than the capacity of the region
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_0_local_clock_reset_block/rxoutclk_bufh_i (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y71

    Clock Rule: rule_bufh_gtx
    Status: PASS
    Rule Description: A BUFH driving a GT must both be in the same clock region
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_0_local_clock_reset_block/rxoutclk_bufh_i (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y71
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_i/U0/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i (GTXE2_CHANNEL.RXUSRCLK) is locked to GTXE2_CHANNEL_X0Y10

    Clock Rule: rule_clk_locked_loads
    Status: PASS
    Rule Description NOT AVAILABLE
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_0_local_clock_reset_block/rxoutclk_bufh_i (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y71
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_i/U0/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i (GTXE2_CHANNEL.RXUSRCLK2) is locked to GTXE2_CHANNEL_X0Y10
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_i/U0/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i (GTXE2_CHANNEL.RXUSRCLK) is locked to GTXE2_CHANNEL_X0Y10

    Clock Rule: rule_gtxcommon_gtxchannel
    Status: PASS
    Rule Description: A GTXCommon driving a GTXChannel must both be in the same clock region
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y2
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_i/U0/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y10

    Clock Rule: rule_bufds_bufg
    Status: PASS
    Rule Description: A BUFDS driving a BUFG must be placed on the same half side (top/bottom) of the device
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_shared_clock_reset_block/ibufds_inst (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y2
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_shared_clock_reset_block/coreclk_bufg_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y30

    Clock Rule: rule_bufds_gtxcommon_intelligent_pin
    Status: PASS
    Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region
    (top/bottom)
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_shared_clock_reset_block/ibufds_inst (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y2
     b_eth_controller/b_10Ge2/ten_gig_eth_pcs_pma_gt_common_block/gtxe2_common_0_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y2

    Clock Rule: rule_gclkio_bufg
    Status: FAIL
    Rule Description: An IOB driving a BUFG must use a CCIO in the same half side (top/bottom) of chip
    as the BUFG
     SI5326_OUT_C_P_IBUF_inst (IBUF.O) is locked to IPAD_X1Y44
     and SI5326_OUT_C_P_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y29
    ERROR: The above is also an illegal clock rule
    Workaround: < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets SI5326_OUT_C_P_IBUF] >

[vemulad]

Hi @geerard

Did you see this error even before inserting ILA in the design?

I see that IPAD_X1Y45 is MGTREFCLK pin. This should be used with transciever blocks in the design. These pins should directly drive IBUFDS_GTE2 primitive which inturn drives the GT blocks in the design. Please check why is the BUFG inserted incorrectly here.

[geerard]

Hi @vemulad,

This pin is a clock input pin, connected to package pin L7 (L8 for non-inverting input), as suggested in the reference XDC file from Xilinx. For now, I've kept the naming conventions in this reference file (this pin is connected to the output of the Si5324[1] chip), although it would be more logical to rename it to Si5324_IN_C_N.

This error was not present when the ILA is not in the design. When I comment the inclusion of the ILA, everything works fine.

Regards,

Dave

[1]: no mistake, Xilinx placed a Si5324 chip on the board but kept the naming of the pins as if it were a Si5326 chip.

[vemulad]

Hi @geerard

Are you connecting this clock Si5324_OUT_C_N input to CLOCK input of ILA?

Is this port SI5326_OUT_C_N meant to drive GT instances in the design?

[geerard]

Hi @vemulad,

The Si5324 clock is indeed driving a GT instance, using a IBUFDS-GTE2-block. The output hereof is used as the clock of the ILA.

Kind regards,

Dave

[vemulad · Accepted solution]

Hi @geerard

But the error says that this port Si5324 is driving a BUFG instance.

Can you opened synthesized design and check what logic is this port Si5324 driving?

[geerard]

Hi @vemulad,

The port is connected to a IBUF instance, of which the output goes to the IBUFDS_GTE2. There was however an attribute to add a BUFG buffer to the input ports. I removed this (since it was deprecated) and now it works.

Thank you.

Dave