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datangel
Contributor
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Registered: ‎09-10-2010

Logic error happens during place_design step in Vivado 2016.1

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Hi everyone,

 

I have met with some logic error in implement when I design a simple Aurora app in Vivado 2016.1. This error only happens when I inserted ILA. It seems as if the truth table of the LUT is changed after place_design step, but the redundant inverter is not removed properly. Have anyone met with this problem? I would be really appreciated if anyone can provide some clue on this.

 

Following is the details. Without ILA, I got this schematic.

 noila.png

When I connect m_axi_rx_tvalid to ILA, I got this schematic. Note that there's one more inverter in this.

 withila.png

The truth table for LUT3 shiftreg_1 in both of these two are the same. It's O=!I0 & !I1 + I1 & I2. So the first one (without ILA connected) is correct under this truth table.

 

I dived deeper into the second design. I found the schematic is the same after opt_design, but the truth table is O=!I0 & I1 + !I1 & I2 . However, it changed to O=!I0 & !I1 + I1 & I2 after place_design. It seems as if the truth table of LUT3 is optimized to include one more inverter into it, but the redundant inverter is not removed due to the existence of ILA connection. Or Vivado should keep the truth table unchanged if it doesn't want to remove the inverter. Could anyone give me some suggestiones on this? Thanks a lot!

 

Best Wishes,

Jonathan

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vemulad
Xilinx Employee
Xilinx Employee
15,831 Views
Registered: ‎09-20-2012

Hi @datangel

 

I see the below message in the log


Phase 1 Placer Initialization

INFO: [Opt 31-138] Pushed 2 inverter(s) to 38 load pin(s).

 

The inverter pushing seems to happen during MLO phase. This can be disabled using below command in 2016.1

 

set_param logicopt.enableMandatoryLopt no

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
9,656 Views
Registered: ‎09-20-2012

Hi @datangel

 

I think the tool is adding the inverter to preseve the net name. Later it adjusted the LUT equation on that path so that the functionality of the design does not change i.e., the output of the LUT remains same before or after inserting ILA.

 

Did you mark this net for debug first using mark_debug constraint?

 

Are you sure that you saw the inverter in the post opt_design checkpoint of design with ILA? 

Thanks,
Deepika.
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datangel
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Registered: ‎09-10-2010

Hi Deepika,

 

Thanks for your quick reply. I am sure the the inverter is there in the post opt_design checkpoint file. I will provide the dcp files if needed. 

 

Best Wishes,

Jonathan

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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi @datangel

 

Please share the post opt dcp.

 

What is the LUT equation in design with no ILA?

Thanks,
Deepika.
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datangel
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Registered: ‎09-10-2010

Hi Deepika,

 

The LUT equation in design without ILA  is O=!I0 & !I1 + I1 & I2. The LUT equation and schematic of post opt_design and post place_design are exactly the same.

I have uploaded post opt/place dcp files in the attachment in case comparing is needed. Please let me know if you need more files of the design. Thanks!

 

Best Wishes,

Jonathan

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vemulad
Xilinx Employee
Xilinx Employee
9,603 Views
Registered: ‎09-20-2012

Hi @datangel

 

I had compared the post opt_design DCP's of designs with ILA and without ILA. In the design with ILA, I see that inverter is added on the path of I1 pin and the LUT equation is modified accordingly. So this is correct behavior.

 

Without ILA:

 

without_ila.PNG

 

With ILA:

 

with_ila.PNG

Thanks,
Deepika.
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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi @datangel

 

Got your point.

 

After running place_design, the LUT equation changes as below but the inverter LUT1 is still present. 

 

after_place.PNG

 

I am checking further on this, will keep you posted.

Thanks,
Deepika.
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datangel
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Registered: ‎09-10-2010

Hi Deepika,

 

Thanks, you are right. The post opt_design is correct. But the post place_design with ILA is uncorrect.  In the post place_design with ILA, LUT equation got changed, but the inverter is still there. 

 

Post_place with ILA:

withila_postplace.png

 

Best Wishes,

Jonathan

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vemulad
Xilinx Employee
Xilinx Employee
9,587 Views
Registered: ‎09-20-2012

Hi @datangel

 

This seems to be a bug in Vivado 2016.1, as a workaround you can use below constraint

 

set_property DONT_TOUCH TRUE [get_cells master2fibre1_ep0/shiftreg_i_1]

 

This issue is not reproducible in Vivado 2016.3 internal build hence I am not filing any CR.

 

 

Thanks,
Deepika.
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datangel
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Registered: ‎09-10-2010

Hi Deepika,

 

In fact, I found two cases in my design which have this kind of problems. Another LUT is adder_block[31].counter[255]_i_1. I am not sure whether there are more cases ignored there.

So could you let me know what's the pattern for this problem? So that I can use above constraint to clear all these problems in my other designs. BTW, is there any timetable for 2016.3? Thanks a lot.

 

Best Wishes,

Jonathan

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vemulad
Xilinx Employee
Xilinx Employee
15,832 Views
Registered: ‎09-20-2012

Hi @datangel

 

I see the below message in the log


Phase 1 Placer Initialization

INFO: [Opt 31-138] Pushed 2 inverter(s) to 38 load pin(s).

 

The inverter pushing seems to happen during MLO phase. This can be disabled using below command in 2016.1

 

set_param logicopt.enableMandatoryLopt no

Thanks,
Deepika.
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datangel
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Registered: ‎09-10-2010

Hi Deepika,

 

Thank you very much for your kindly help. I have tried the set_param command and I think it cleared all problems.

 

Best Wishes,

Jonathan

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