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abbey_
Participant
Participant
349 Views
Registered: ‎12-16-2020

Logical ports error on vivado

Hi, 

 

I am trying to generate a bit stream in vivado but i get this error: 

[DRC NSTD-1] Unspecified I/O Standard: 38 out of 38 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: gateway_out[15:0], gateway_in[15:0], and gateway_in1[5:0].

[DRC UCIO-1] Unconstrained Logical Port: 38 out of 38 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: gateway_out[15:0], gateway_in[15:0], and gateway_in1[5:0].

How do I resolve this?

Kind regards, 
Abbey

 

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3 Replies
joancab
Advisor
Advisor
336 Views
Registered: ‎05-11-2015

You have your design with logical inputs and outputs, fine, but you still have to tell Vivado:

1. What pin is to be connected to each of your top file ports. Second error (38 out of 38 logical ports have no user assigned specific location constraint)

2. What standard (LVCMOS, etc.) will each of those pins use. First error (Unspecified I/O Standard).

You need to add a constraints file. I suppose you know nothing about this. No problem, we all have been there some time.

There is a Constraints user guide you may refer in the future, but for the time being a quick way to constraint your design is:

1. Run Synthesis (not implementation)

2. Open the synthesized design

3. On the top, click Layout > I/O planning

You should see a drawing of the chip and a list of ports (I have none here, but you should have)

joancab_1-1616428586750.png

4. For each port, select the standard in the corresponding column (drop down)

5. Drag each port in the list to the physical pin you want it to be.

6. Repeat 4, 5 until done.

7. Save or CTRL-S. You will be asked whether to attach that to an existent constraints file or create a new one. Go for the second and give it a name (I'm never too original and always name it 'constraints')

8. Generate the bitstream. Your pain should be gone.

Bonus point: look (open) at the generated constraints file and learn how pin locations and standards are assigned. 

abbey_
Participant
Participant
268 Views
Registered: ‎12-16-2020

Hi @joancab 

Thank you for the reply, should system generator not do this automatically? or do all of the ports still need to be selected via the method above?

Thanks,
Abbey

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joancab
Advisor
Advisor
261 Views
Registered: ‎05-11-2015

No, that's a schematic information, Vivado cannot know. The way to add it to Vivado is via the constraints file.

For a custom board, it has to be done manually, either as above or typing constraints straight away. For many of the shelf development boards they provide a master constraints file (but bear in mind your port names must match the names on the intended pins, or else the names in the constraint file changed to match your names)