Re: Lutram packing error

viktorpus · ‎03-14-2014

Hello,

When I synthesize one of my designs for Virtex-7 (xc7vx690tffg1157-2) using Vivado, I sometimes get the following error:

ERROR: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed.

Number of LUTRAMs: 53244

Number of LUTRAM capable slices required is 21721 out of 43550 in the device (utilization 49.876%)

Even though there is a sufficient number of LUTRAM capable slices in the device, the packing algorithm was not able to find a solution. Please analyze your design to determine if the number of LUTRAMs can be reduced.

As a result, 5 LUTRAMs failed to place.

Names of these LUTRAMs:

pcs_pma_i/TEN_TEN_GEN.ETH_PHY_10_1[1].ETH_PHY_10/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_core/ten_gig_eth_pcs_pma_inst/G_IS_V7GTH.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/ten_gig_disti_ram_reg_0_31_24_29 type RAM32M

pcs_pma_i/TEN_TEN_GEN.ETH_PHY_10_1[1].ETH_PHY_10/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_core/ten_gig_eth_pcs_pma_inst/G_IS_V7GTH.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/ten_gig_disti_ram_reg_0_31_36_41 type RAM32M

pcs_pma_i/TEN_TEN_GEN.ETH_PHY_10_1[1].ETH_PHY_10/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_core/ten_gig_eth_pcs_pma_inst/G_IS_V7GTH.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/ten_gig_disti_ram_reg_0_31_48_53 type RAM32M

pcs_pma_i/TEN_TEN_GEN.ETH_PHY_10_1[1].ETH_PHY_10/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_core/ten_gig_eth_pcs_pma_inst/G_IS_V7GTH.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/ten_gig_disti_ram_reg_0_31_66_71 type RAM32M

pcs_pma_i/TEN_TEN_GEN.ETH_PHY_10_1[1].ETH_PHY_10/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_core/ten_gig_eth_pcs_pma_inst/G_IS_V7GTH.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/ten_gig_disti_ram_reg_0_31_6_11 type RAM32M

The mentioned LUTRAMs are constrained as below: (listing maximum of 20 LUTRAMs per constraint)

An interal area constraint:

pcs_pma_i/TEN_TEN_GEN.ETH_PHY_10_1[1].ETH_PHY_10/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_core/ten_gig_eth_pcs_pma_inst/G_IS_V7GTH.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/ten_gig_disti_ram_reg_0_31_24_29

pcs_pma_i/TEN_TEN_GEN.ETH_PHY_10_1[1].ETH_PHY_10/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_core/ten_gig_eth_pcs_pma_inst/G_IS_V7GTH.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/ten_gig_disti_ram_reg_0_31_36_41

pcs_pma_i/TEN_TEN_GEN.ETH_PHY_10_1[1].ETH_PHY_10/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_core/ten_gig_eth_pcs_pma_inst/G_IS_V7GTH.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/ten_gig_disti_ram_reg_0_31_48_53

pcs_pma_i/TEN_TEN_GEN.ETH_PHY_10_1[1].ETH_PHY_10/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_core/ten_gig_eth_pcs_pma_inst/G_IS_V7GTH.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/ten_gig_disti_ram_reg_0_31_66_71

pcs_pma_i/TEN_TEN_GEN.ETH_PHY_10_1[1].ETH_PHY_10/ten_gig_eth_pcs_pma_i/U0/ten_gig_eth_pcs_pma_core/ten_gig_eth_pcs_pma_inst/G_IS_V7GTH.ten_gig_eth_pcs_pma_inst/ten_gig_eth_pcs_pma_inst/rx_elastic_buffer_i/asynch_fifo_i/dp_ram_i/ten_gig_disti_ram_reg_0_31_6_11

Number of LUTRAMs required* by this constraint: 48

Number of LUTRAMs available in this constraint region: 9900

Utilization = 0% (Worst Case Utilization = 0% )

* - The number of LUTRAMs required is computed under assumption that the LUTRAMs can be perfectly packed in the constrained region. Also, each LUTRAM may be a macro containing multiple LUTRAM instances.

Resolution: Please analyze your design to determine if the number of lutrams can be reduced by combining multiple lutrams into Block RAMs for example.

The actual number of failed LUTRAMs vary (from 2 to 6), but their position within my design is always the same – inside ten_gig_eth_pcs_pma IP core from Xilinx. For me the weird part of this error is that there should be enough space to place few more LUTRAMs (the total LUTRAM utilizations shown is under 50%). Furthermore, I encountered this error for the first time after some code optimizations which actually reduced the number of used logic resources including LUTRAMs.

Can anyone please tell me what can cause this error and how to resolve it? Or at least explain, how can the placement process fail when there are still more than half of the FPGA unused?

Thank you,

Viktor

austin · ‎03-14-2014

v,

Regardless of the resource usage (5% or 95%) there may be un-routable designs (choices of placement) because to meet all of the constraints, the design as placed, runs out of interconnection resources (the design cannot be routed).

The more the design is constrained (IO, timing, locating blocks physically...) the harder it gets for the tools to complete the placement and routing successfully.

Austin Lesea
Principal Engineer
Xilinx San Jose

bwade · ‎03-14-2014

What are the control sets for the LUTRAM like? That may be what's preventing the placer from reaching higher placement density.

viktorpus · ‎03-18-2014

Hello,

the design has 3482 unique control sets for xc7vx690tffg1157-2. Is that a reasonable value?

The error reports that the design has 53244 LUTRAMs and that it requires 21721 LUTRAM capable slices. That means that in average 2.45 LUTRAMs are packed into one LUTRAM capable slice (out of 4 maximal).

Thanks,

Viktor