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Registered: ‎06-30-2016

MAP Error with planAhead/Hard Macro

I created a hard macro with PlanAhead 14.7. This is a AND gate, very easy.  I have used -uc to LOC constraints for the slices placed in the ucf and using the -sd switch at the ngdbuild stage to point to the .nmc file. But when I run MAP, there is a Error,:"[Place 835] Given the original pre-placement, no legal placements can be found for 1 group(s). The following is the description of these group(s). The relative offsets of the components are shown in brackets next to the component names.
     LUT AND_test_inst/C_OBUF (0, 0)
     LUT AND_test_inst/C_OBUF (0, 0)
     LUT AND_test_inst/C_OBUF (0, 0)
     LUT AND_test_inst/C_OBUF (0, 0)
     LUT AND_test_inst/C_OBUF (0, 0)
     LUT AND_test_inst/C_OBUF (0, 0)
     LUT AND_test_inst/C_OBUF (0, 0)
     LUT AND_test_inst/C_OBUF (0, 0)
     FF AND_test_inst/C_OBUF (0, 0)
     FF AND_test_inst/C_OBUF (0, 0)
     FF AND_test_inst/C_OBUF (0, 0)
     FF AND_test_inst/C_OBUF (0, 0)
     FF AND_test_inst/C_OBUF (0, 0)
     FF AND_test_inst/C_OBUF (0, 0)
     FF AND_test_inst/C_OBUF (0, 0)
     FF AND_test_inst/C_OBUF (0, 0)"

 

I dont know why.

 

and another question,

In LOC file, I write

"NET "A_in_IBUF" LOC = AA34;
NET "B_in_IBUF" LOC = AA33;
NET "C_out_OBUF" LOC = AA30;"

no warning, but only Error in MAP.

 

But when I write "INST "AND_test_inst" LOC = SLICE_X0Y78;"

there is another Warning " [Constraints 18-5] Cannot loc instance 'AND_test_inst' at site SLICE_X0Y78, AND_test_inst is not a leaf level instance [/localtemp/yzhang/uemu/ml605_core_vfsm_subsystem/syn/project_AND_test/project_AND_test.srcs/constrs_1/new/AND_test_subsystem.ucf:2]"

 

Pls help me, thanks a lot.





 

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Registered: ‎11-23-2017

Re: MAP Error with planAhead/Hard Macro

Hello, I have the same problem. I have a hard macro and I have the same error, but only with Virtex, 4, Virtex 5 and Spartan3E models does not appear that problem.

Did you find any solution?

Regards.

 

L. Adolfo. Luna

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