02-26-2013 10:57 PM
I am having the following error while doing Mapping phase of the design...But I can't understand why previously I did not get this error.
ERROR:PhysDesignRules:2216 - IDELAYCTRL not found for clock region CLOCKREGION_X0Y2. The IODELAYE1 block fmc10x_io_buf_adc_inst/fmc10x_io_buf_data_ab/chb_lvds_bufs.data_b.iodelay_inst has an IDELAY_TYPE attribute of FIXED, VARIABLE, or VAR_LOADABLE. This programming requires that there be an IDELAYCTRL block programmed within the same clock region.
Now I understand that I have to insert IDELAYCTRL somewhere, but previously I never added this in the reference design that I am using.
and that design worked fine since it was provided by the company who provided the board and reference designs...
Now that I change only my code for storing and retreiving data and so on without changing the parts which are responsible for communication with
ADC, i.e. I did not changed IBUFDS and IODELAYE1 etc. things since I have only bookish idea of these things...
Then why am I getting these errors...
Also how to deal with these errors now that I am having it (of course I am looking for material but any expert solution would be helpful)
By the way the code snippet is as below...
-- Use LVDS buffers in HPC and LPC mode when LVDS is selected cha_lvds_bufs: if (CMOS_N_LVDS = '0') generate data_a: for i in 0 to RESOLUTION/2-1 generate -- Differantial input buffer ibufds_inst : ibufds generic map ( IOSTANDARD => "LVDS_25", DIFF_TERM => TRUE ) port map ( i => cha_p(i), ib => cha_n(i), o => cha_ddr(i) ); -- Input delay iodelay_inst : iodelaye1 generic map ( IDELAY_TYPE => "VARIABLE",--"FIXED", IDELAY_VALUE => CHA_IDELAY, DELAY_src=> "I" ) port map ( DATAOUT => cha_ddr_dly(i), IDATAIN => cha_ddr(i), c => clk, ce => ce_a, inc => inc_a, datain => '0', odatain => '0', clkin => '0', rst => rst, cntvaluein => conv_std_logic_vector(CHA_IDELAY, 5), cinvctrl => '0', t => '1' ); -- DDR to SDR iddr_inst : iddr generic map ( DDR_CLK_EDGE => "SAME_EDGE_PIPELINED" ) port map ( q1 => cha_sdr(2*i), q2 => cha_sdr(2*i+1), c => clk_ab, ce => '1', d => cha_ddr_dly(i), r => '0', s => '0' ); end generate; end generate cha_lvds_bufs;
Also if it has to be apllied in any case, then how? can you show me the example
02-27-2013 01:12 AM - edited 02-27-2013 01:14 AM
When ever you are setting the IDELAY_TYPE to fixed,variable or VAR_LOADABLE, you must instantiate the IDELAYCTRL in the design.
Refer to page-103,112 of http://www.xilinx.com/support/documentation/user_guides/ug361.pdf for more details.
02-27-2013 04:50 AM - edited 02-27-2013 04:51 AM
Yes that I know. But how to introduce it sinceI use it first time and as I mentioned in previous email. When I use the reference design and make slight changes as well there was no problem, but now without disturbing the 'entity for the relevant hardware or block ' it shows problem...
Yes that I understand, but I cannot understand how to instantiate it and where to connect the instantiated input and output.
e.g. In the figure below how to and to which port of which component I should connect the RDY, REFCLK is I think the adc clock, while RSST is system's reset.
Figure below is taken from ug361. I also looked for instantiation template in virtex 6 hdl instantiated template but could not find
02-27-2013 06:27 AM - edited 02-27-2013 07:03 AM
You can find the instantiation template for IDELAYCTRL in language templates.
In ISE Project Navigator goto Edit --> Language Templates. You can find this IDELAYCTRL under language/ Device Primitive instantiation / Device / IO components / IDELAYCTRL.
IDELAYCTRL IDELAYCTRL_inst (
.RDY(RDY), // 1-bit Ready output
.REFCLK(REFCLK), // 1-bit Reference clock input
.RST(RST) // 1-bit Reset input
The RDY is a status signal which indicates that the IDELAY elements are being calibrated. You can leave this unconnected/connect it to GND or you can connect it to output port.
For better understanding you can use select IO wizard and generate the core. Now check the code generated for the core. It will have IDELAY and IDELAYCTRL instantiated. You can use this reference and build up your own code.
02-27-2013 09:18 AM
No new IODELAYs were added to the design? If so, then something has gone wrong with the original IODELAY configuration, but the solution depends on what IDELAYCTRL strategy is being used. Is there more than one IODELAY_GROUP in the design? Are the IDELAYCTRLs constrained?
- If the IDELAYCTRL is constrained and the bank usage has been modified or has increased, then it is up to you to replicate the IDELAYCTRL or change the constraint manually. If you can move the IO in the error message to a bank that already has an IDELAYCTRL that would also work.
- If the IDELAYCTRL is unconstrained, then the placer should be replicating the the IDELAYCTRL to all IO Banks that need one. If it is failing to do that then that's a bug and you may want to switch to the manual technique.
- If there are multiple IODELAY_GROUPs then that complicates things. Here is an Answer Record that discusses the various IDELAYCTRL group strategies: