cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mehrdadfeller
Visitor
Visitor
11,531 Views
Registered: ‎05-17-2008

MAP modifies my LUT function and removes nets

Hi guys,

 

I know that this is a common problem but mine is a bit different. I am implementing a non-conventional circuit as follows:

 

I am instantiating an LUT that implements a buffer Out=A1. The function of the LUT is not dependent on other LUT inputs. In other words,the rest of the inputs are don't cares, but I would like to keep them in my design. Here is my module:

 

-------------------------------------

module control(A1,Out, T);

 

input A1, T;

output Out;

 

LUT6 #(
.INIT(64'haaaaaaaaaaaaaaaa) // This implement a buffer hex a=binary 1010
) LUT6_inst (
.O(Out), // LUT general output
.I0(A1), // LUT input
.I1(T), // LUT input
.I2(T), // LUT input
.I3(T), // LUT input
.I4(T), // LUT input
.I5(T) // LUT input
);

 

endmodule

-------------------------------------

 

The rest of the inputs are being connected to each other (net "t") and controlled by another logic gate.

 

In my UCF file, I specify the following location constaint:

INST ".../LUT6_inst" LOC = "SLICE_X17Y27";

 

Now when the design is synthesize, I see the LUT in the RTL/Technology schematic the way I want...but what comes after MAP and PAR does not include the "T" net, which is apparently optimized out. In other word, the physical design view on FPGA editor is the LUT with only one input (A1), and there is no sign of the net "T".

 

More weired is that in the MAP report there is nothing any nets being removed...!

 

I searched a little bit and added the following MAP/Synthesis constaints but the problems still persists:

 

-------------------------------------

module control(A1,Out, T);

 

(* KEEP = "TRUE" *) (* S = "TRUE" *) input A1, T;

(* KEEP = "TRUE" *) (* S = "TRUE" *) output Out;

 

(* LOCK_PINS = "all" *) LUT6 #(

.INIT(64'haaaaaaaaaaaaaaaa) // Specify LUT Contents
) LUT6_inst (
.O(Out), // LUT general output
.I0(A1), // LUT input
.I1(T), // LUT input
.I2(T), // LUT input
.I3(T), // LUT input
.I4(T), // LUT input
.I5(T) // LUT input
);

 

endmodule

-------------------------------------

 

I also tried adding the following to the UCF file instead of the verilog source to no avail.

NET netname KEEP;

NET netname S;

 

BTW, I am using Xilinx ISE Pack 11.4.

 

I would really appreciate your Help!

Thanks,

Mehrdad

 

0 Kudos
8 Replies
bwade
Scholar
Scholar
11,504 Views
Registered: ‎07-01-2008

Have you tried LOCK_PINS in the UCF file?

 

INST ".../LUT6_inst" LOCK_PINS; 

 

I use this pretty frequently and would be surprised if it doesn't work. Are you using any Global Opt features during MAP? That might be an issue.

0 Kudos
mehrdadfeller
Visitor
Visitor
11,499 Views
Registered: ‎05-17-2008

Thanks for the reply.

 

This is just driving me insane :(...

 

I have tried insering the constraints in both UCF and Verilog and they act the same way, and the issue exists.

 

I also tried instantiating buffers in my design and enforcing to keep the nets but still no progress.

 

This is the verilog code that has the buffers in it:

 

-----------------------------------------------------------------------------------------

`timescale 1ns / 1ps

module pdl_block(i,o,t);

(* S = "TRUE" *) input i;
(* S = "TRUE" *) input t;
(* S = "TRUE" *) output o;
wire  wi, wt;


(* S = "TRUE" *) IBUF #(
.IBUF_DELAY_VALUE("0"),
.IFD_DELAY_VALUE("AUTO"),
.IOSTANDARD("DEFAULT")
)IBUF_inst_1 (
.O(wi), // Buffer output
.I(i) // Buffer input (connect directly to top-level port)
);


(* S = "TRUE" *) IBUF #(
.IBUF_DELAY_VALUE("0"),
.IFD_DELAY_VALUE("AUTO"),
.IOSTANDARD("DEFAULT")
)IBUF_inst_2 (
.O(wt), // Buffer output
.I(t) // Buffer input (connect directly to top-level port)
);


//(* BEL ="D6LUT", LOCK_PINS = "ALL", S = "TRUE" *)

LUT6 #(
.INIT(64'h5555555555555555) // Specify LUT Contents
) LUT6_inst (
.O(o), // LUT general output
.I0(wi), // LUT input
.I1(wt), // LUT input
.I2(wt), // LUT input
.I3(wt), // LUT input
.I4(wt), // LUT input
.I5(wt) // LUT input
);
// End of LUT6_inst instantiation

endmodule

------------------------------------------------------------------------------------------

 

 

and this is the content of my UCF file:

 

INST "LUT6_inst" LOC = "SLICE_X17Y73";
INST "LUT6_inst" LOCK_PINS;
INST "LUT6_inst" S;
INST "LUT6_inst" BEL="D6LUT";

NET "wt" S;
NET "wi" S;

NET "i" LOC="U25";
NET "t" LOC="AG27";
NET "o" LOC="AF13";
-----------------------------------------------------------------------------------------------

 

I see the following warning in MAP report (which didn't pop up before..kinda wierd) but it's refering to the problem:

 

Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:367 - The signal <wt> is incomplete. The signal does not
   drive any load pins in the design.

 

and also:

 

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:950 - SAVE has been detected on block "IBUF_inst_1"
INFO:MapLib:950 - SAVE has been detected on block "IBUF_inst_2"
INFO:MapLib:950 - SAVE has been detected on block "LUT6_inst"

 

 

 

 

I checked the option on MAP and the optimizations are not active:

 

map -ise Single_PDL.ise -intstyle ise -p xc5vlx110t-ff1136-3 -w -logic_opt off -ol std -t 1 -register_duplication off -global_opt off -mt off -detail -ir off -pr off -u -lc area -power off -o pdl_block_map.ncd

 

 

:(((

 

 

 

0 Kudos
mehrdadfeller
Visitor
Visitor
11,498 Views
Registered: ‎05-17-2008

Please also see the Technology Schematic View attached

6-7-2010 7-12-31 PM.jpg
0 Kudos
ahmed_elnably
Newbie
Newbie
11,462 Views
Registered: ‎06-08-2010

It seems that ISE check that the output of the LUT doesn't depend on the t signal, so it just optimize it.

So for this specific case where t can only be 0 or 1, i.e. you will only use the LUT values all zeros, all ones, 0 in MSb and others are ones, and 1 in MSb and others are zeros. you can simply change any value of the LUT so that it acts as an inverter

for example other than intializing the LUT with 64'h5555555555555555 you can intialized it with 64'h5655555555555555, like that the ISE will know that you need to keep track the value of the input, and it will not optimize it.

 

Ahmed

0 Kudos
bwade
Scholar
Scholar
11,394 Views
Registered: ‎07-01-2008

If all else fails, a hard macro (.nmc) could be used to implement the circuit. I would start with a small design that includes a LUT with a LOCK_PINS constraint applied to it and then modify that into the circuit you want before saving as a hard macro. The reason I say that is it's hard to apply the constraint to an existing macro, you have to hack it using XDL.

0 Kudos
mehrdadfeller
Visitor
Visitor
11,390 Views
Registered: ‎05-17-2008

thanks Jim, Ahmed, and bwade for your response...

 

I have been able to find a way to go around the issue but I would be still interested to see other solutions.

 

What I did was very similar to Ahmed approach with same modification inside XDL files. So here is my approach:

 

I use some arbitrary initialization for the LUT for which the constant optimization keeps my nets. For example in my case, using the initialization INIT=64'h5655555555555555 for the LUT keep the net T that goes to all pins (I am still using lock_pins, s, keep constaints as mentioned in previous posts).

 

After doing the sythesis and implementation, I run the following command to generate XDL file:

 

xdl -ncd2xdl filename.ncd

 

then I open the generated filename.xdl file in an text editor and search for:

 

((~A1*(A2+(A3+(~A4+(~A5+~A6)))))+(A1*(~A2*(~A3*(A4*(A5*A6))))))

 

and replace that with whatever function I want. Then I save the changes to XDL file and run:

 

xdl -xdl2ncd filename.ncd

 

to make sure the changes are saved I open the ncd file inside FPGA Editor and make sure the changes have taken placed.

 

There is however a danger in the approach that is you may unintentionally change the function of some other LUTs that match your description in your design...so you should be careful with what you are chaging inside XDL or otherwise your design will not work the way you want.

 

 

0 Kudos
mehrdadfeller
Visitor
Visitor
11,389 Views
Registered: ‎05-17-2008

by the way bwade,

 

I am not sure if I completely understand your approach...could you please elaborate more?

 

Thanks,

Mehrdad

0 Kudos
bwade
Scholar
Scholar
11,342 Views
Registered: ‎07-01-2008

Hi Mehrdad,

 

Regarding the hard macro approach, hard macros are physical macros that are created in fpga editor either from scratch or from an existing mapped NCD.  Usually it's best to use an RPM macro in the logical design to control packing and placement but the hard macro can be useful to implement logic that you can't otherwise get the tools to accept. The macro is a black box to map and will not be trimmed or optimized in any way. The router will however pinswap LUT pins in hard macro slices so if that's an issue, there's no direct way to apply the constraints to the macro LUTs since they don't get processed by ngdbuild/map. Here's a CAF discussion of this subject:

 

http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/510e4357498dff48/155501919d966c78?hl=en&q=LOCK_PINS+group:comp.arch.fpga+author:Bret#155501919d966c78

 

User documentation is here:

http://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/fpga_editor/fpga_editor.htm

See the  "Using Macros" section.

0 Kudos