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Adventurer
Adventurer
3,247 Views
Registered: ‎06-05-2012

MAP problems after simulation

I am doing a project about image processing. My colleague finished the interface part, and after verification on board, it works well. I am doing the algm part, before my work, I want to build the testbench for the interface part to see its internal signal. But, after I building the testbench, implement this former project again. It got some MAP problem. as follows:  

 

Place:1333 - Following IOB's that have input/output programming are locked to the bank 1 that does not support such values
IO Standard: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = BIDIR, DRIVE_STR = NR
List of locked IOB's:
MCB1_DDR3_XDQS<0>
MCB1_DDR3_XDQS<1>
MCB1_DDR3_DQS<0>
MCB1_DDR3_DQS<1>

 

after moving the testbench, the problem still exist. I have no idea about it. It seems the testbench changes something in uut.

 

ps: in this project, mig core is used. and the chip is spartan-6

 

Thank you everybody.

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2 Replies
Xilinx Employee
Xilinx Employee
3,235 Views
Registered: ‎07-16-2008

Re: MAP problems after simulation

I'll move it to implementation forum as it's a placer error.

 

A testbench shouldn't cause such kind of issue.

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Xilinx Employee
Xilinx Employee
3,211 Views
Registered: ‎02-11-2010

Re: MAP problems after simulation

The addition of a testbench should not cause the implementation to change for the design. Are you sure the uut has not been modified and that all implementation options are still the same as the error free implementation? If that is the case perhaps you should open a webcase with Xilinx tech support.
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