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Observer
Observer
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Registered: ‎07-24-2018

MIG 7 series DDR3 HR banks implementation errors - 2 Controllers / 2 DDR3 SDRAM

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Hi,
We try to implement a MIG 7 series with 2 controllers and 2 DDR3 SDRAM on a Zynq-7100 which provides 3 HP Banks.

When we try to implement the MIG, we are not able to successfullly place&route the design

QUESTION : Is it possible to shared an HP Bank between 2 MIG controllers ?

Default MIG Wizard provides following setting :
for Controller 0 - DDR3 SDRAM on Bank 35 and Bank 34

- Address/Ctrl-0-1-2 ==> Bank 35 - Byte Groupe T0-T1-T2
- DQ[0-7] ==> Bank 35 - Byte Groupe T3
- DQ[8-15] ==> Bank 34 - Byte Groupe T1

for Controller 1 - DDR3 SDRAM, only Bank 33 is free so we cannot set all signals groups

Trick/Alternative_1 : If we use custom DDR3 pinouts with '.ucf' files {Fixed Pin Out : Pre-existing pin out is known and fixed},
and bypass a load file IHM bug, we obtain placement error
set_property LOC PHY_CONTROL_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]

How can we fix this error ?


Trick/Alternative_2 :
We have tried a version which implements 2 MIGs with each one 1 controller and 1 DDR3 SDRAM, same trouble during implementation :

[Vivado 12-2285] Cannot set LOC property of instance 'U0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i'...
Instance U0/u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i
can not be placed in PHY_CONTROL of site PHY_CONTROL_X1Y5
because the bel is occupied by U1/u_mig_7series_1_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i(port:).
This could be caused by bel constraint conflict ["c:/WORK_XILINX/MIG_DDR3_Z7100/MIG_DDR3_Z7100_2CTRL_2MIG_2DDR/mig2_without_axi.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc":363]

[DRC PLIDC-4] IDELAYCTRL IODELAYs with conflicting groups for same bank: Found IODELAY cells with different IODELAY group constraints for same I/O bank 34.
The IODELAY cells and its group constrained to this bank are:
'U0/u_mig_7series_0_mig/u_memc_ui_top_std/..../ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 : MIG_7SERIES_0_IODELAY_MIG1'
'U1/u_mig_7series_1_mig/u_memc_ui_top_std/.../ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 : MIG_7SERIES_1_IODELAY_MIG1'


... even if we force MIG_7SERIES_0_IODELAY_MIG0/1 of 2 MIG (U0 & U1) by TCL constraints, we cannot solve IDELAYCTRL IODELAY error

How can we fix theses errors ? Cannot find recommendations about a double MIG usage

For information, following picture represents wanted Zynq-7100 MIG-DDR3 configuration :

Capture.JPG

 

Configuration
FPGA : Zynq-7000 (xc7z100iffg1156-2L)
DDR3 Reference : MT41K256M16XX-125 (16 Bits)
XILINX : Vivado 2018.3 (Win10)


Note : For performance reasons, we dont want to use HR banks but only x3 HP Banks

Regards

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Xilinx Employee
Xilinx Employee
314 Views
Registered: ‎05-22-2018

Re: MIG 7 series DDR3 HR banks implementation errors - 2 Controllers / 2 DDR3 SDRAM

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Hi @erems ,

Glad to know issue resolved.

Do you have further queries on this? If not, please close this thread by marking it as accepted solution. 

Thanks,

Raj

View solution in original post

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Observer
Observer
327 Views
Registered: ‎07-24-2018

Re: MIG 7 series DDR3 HR banks implementation errors - 2 Controllers / 2 DDR3 SDRAM

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Auto-reply

Solution found in AR# 41706 (MIG 7 Series - Can FPGA banks be shared among memory interfaces)

  • FPGA banks cannot be shared between multiple memory controllers.
  • Each MIG interface requires a unique PHY Control Block in all interface banks.
  • The PHY Control Block is dedicated logic that controls the FIFOs and Phasers within the bank.
  • Both Address/Control and Data Byte Groups use the PHY Control Block within the bank and only one PHY Control Block exists in an FPGA bank.
  • Therefore, it is not possible to share a bank between two interfaces.

BR

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Xilinx Employee
Xilinx Employee
315 Views
Registered: ‎05-22-2018

Re: MIG 7 series DDR3 HR banks implementation errors - 2 Controllers / 2 DDR3 SDRAM

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Hi @erems ,

Glad to know issue resolved.

Do you have further queries on this? If not, please close this thread by marking it as accepted solution. 

Thanks,

Raj

View solution in original post

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Observer
Observer
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Registered: ‎07-24-2018

Re: MIG 7 series DDR3 HR banks implementation errors - 2 Controllers / 2 DDR3 SDRAM

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Close topic - Solved

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