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Observer hillseg
Observer
315 Views
Registered: ‎06-01-2016

MUXing 4:1 GTX clock unroutable placement

Hi everyone!
I have an issue with multiplexing GTX clock's from four independent receivers and I need to switch between them to communicate with other part of the logic.

At the picture simplified part of what i'm trying to do.

FPGA that i use is Virtex-6 (XC6VSX315T-2FF1759), ISE Design Suite 14.7

I use 3 bufgmux_ctrl to muxing rxusrclk2 (180MHz) clock that goes from the mmcm block. It is seems to me alright but at the mapping part it occurs error:

ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
pair have been found that are not placed at a routable site pair. The driver
BUFGCTRL component <GTX_WRAPPER_INST/GTX_MUX_INST/BufGCtrlMuxA_l> is placed
at site <BUFGCTRL_X0Y0>. The load BUFGCTRL component
<GTX_WRAPPER_INST/GTX_MUX_INST/BufGCtrlMux_l> is placed at site
<BUFGCTRL_X0Y24>. The BUFGCTRL components can use the fast path between them
if they are placed in adjacent BUFGCTRL sites, and both are in the same half
of the device (TOP or BOTTOM). You may want to analyze why this problem
exists and correct it. This placement is UNROUTABLE in PAR and therefore,
this error condition should be fixed in your design. You may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING in order to generate an NCD file. This NCD file can then be used in
FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
clock placement rule is listed below. These examples can be used directly in
the .ucf file to demote this ERROR to a WARNING.
ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component
pair have been found that are not placed at a routable site pair. The driver
BUFGCTRL component <GTX_WRAPPER_INST/GTX_MUX_INST/BufGCtrlMuxB_l> is placed
at site <BUFGCTRL_X0Y18>. The load BUFGCTRL component
<GTX_WRAPPER_INST/GTX_MUX_INST/BufGCtrlMux_l> is placed at site
<BUFGCTRL_X0Y24>. The BUFGCTRL components can use the fast path between them
if they are placed in adjacent BUFGCTRL sites, and both are in the same half
of the device (TOP or BOTTOM). You may want to analyze why this problem
exists and correct it. This placement is UNROUTABLE in PAR and therefore,
this error condition should be fixed in your design. You may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING in order to generate an NCD file. This NCD file can then be used in
FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
clock placement rule is listed below. These examples can be used directly in
the .ucf file to demote this ERROR to a WARNING.

Here is a part of the MUX code:

 

...    
    BufGCtrlMuxA_l : BUFGMUX_CTRL port map(S => SEL_IN(0), I0 => REFCLK_IN(0), I1 => REFCLK_IN(1), O => mux_0);
    BufGCtrlMuxB_l : BUFGMUX_CTRL port map(S => SEL_IN(0), I0 => REFCLK_IN(2), I1 => REFCLK_IN(3), O => mux_1);
    BufGCtrlMux_l  : BUFGMUX_CTRL port map(S => SEL_IN(1), I0 => mux_0, I1 => mux_1, O => REFCLK_OUT);
...

 

 

And if i trying to LOC this BUFGCTRL_X0Y24 and BUFGCTRL_X0Y18 or BUFGCTRL_X0Y0 and BUFGCTRL_X0Y24 primitive closer together same problem happened with the placement BUFGMUX_CTRL and output of the MMCM block.

I read post's that says that i need to CLOCK_DEDICATED_ROUTE some pins but i can't figure it out how to do this

 

# PIN "GTX_WRAPPER_INST/GTX_MUX_INST/BufGCtrlMuxA_l/BUFGMUX_CTRL.I0" CLOCK_DEDICATED_ROUTE = FALSE;
# PIN "GTX_WRAPPER_INST/GTX_MUX_INST/BufGCtrlMuxA_l/BUFGMUX_CTRL.I1" CLOCK_DEDICATED_ROUTE = FALSE;

It's doesn't work.

MMCM setting's is 360 input clock (global buffer), output 360 and 180 drives BUFG (i'll tried BUFH or without any buffer at all still nothing's changed)

 

 

Here is the part of the UCF file:

 
INST "GTX_WRAPPER_INST/GTX_INIT_INST/gtx_channel[0].gtx_i/gtxe1_i" LOC = GTXE1_X0Y12;
INST "GTX_WRAPPER_INST/GTX_INIT_INST/gtx_channel[1].gtx_i/gtxe1_i" LOC = GTXE1_X0Y13;
INST "GTX_WRAPPER_INST/GTX_INIT_INST/gtx_channel[2].gtx_i/gtxe1_i" LOC = GTXE1_X0Y14;
INST "GTX_WRAPPER_INST/GTX_INIT_INST/gtx_channel[3].gtx_i/gtxe1_i" LOC = GTXE1_X0Y15;

INST "GTX_WRAPPER_INST/GTX_MUX_INST/BufGCtrlMuxB_l" LOC = BUFGCTRL_X0Y21; # X0Y1
INST "GTX_WRAPPER_INST/GTX_MUX_INST/BufGCtrlMux_l"  LOC = BUFGCTRL_X0Y22; # X0Y2
INST "GTX_WRAPPER_INST/GTX_MUX_INST/BufGCtrlMuxA_l" LOC = BUFGCTRL_X0Y23; # X0Y3
INST "GTX_WRAPPER_INST/GTX_SLIDE_INST[0].RXCLK_MMCM_INST/clkout2_buf" LOC = BUFGCTRL_X0Y24;
INST "GTX_WRAPPER_INST/GTX_SLIDE_INST[1].RXCLK_MMCM_INST/clkout2_buf" LOC = BUFGCTRL_X0Y25;
INST "GTX_WRAPPER_INST/GTX_SLIDE_INST[2].RXCLK_MMCM_INST/clkout2_buf" LOC = BUFGCTRL_X0Y26;
INST "GTX_WRAPPER_INST/GTX_SLIDE_INST[3].RXCLK_MMCM_INST/clkout2_buf" LOC = BUFGCTRL_X0Y27;
Can someone to guide me how to solve this problem? And why this happened?
scheme.png
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2 Replies
Xilinx Employee
Xilinx Employee
275 Views
Registered: ‎05-08-2012

Re: MUXing 4:1 GTX clock unroutable placement

Hi @hillseg 

 

The BUFGs don't just need to be close, but adjacent. The Methodology GUide also has some good suggestions on muxing clocks.

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug949-vivado-design-methodology.pdf


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Observer hillseg
Observer
204 Views
Registered: ‎06-01-2016

Re: MUXing 4:1 GTX clock unroutable placement

So my option is on page 112, but how do i constraint this on virtex-6 (or anytihng else thats work under ISE Design)?

There's nothing to say how to do this, just abstarct.

I created a project that replicate my issue, may be someone already solved this problem

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