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Visitor
Visitor
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Registered: ‎02-20-2014

Make MAP use dedicated hardware from behavioral code

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Hi,

I've written a 32 bit synchronous adder in VHDL with behavioral description. I'm implementing the design for a Spartan-6, and I would like to use the DSP48A1 slice instead of general logics. After synthesis, I see a 32 bit asynchronous adder and a 32 bit register. After implementation, I get only LUTs instead of a DSP slice. Someone told me there is a guide about writing such code that the tools will recognize as dedicated hardware. I'm speaking about behavioural description, I know it can be also done with structural description with instantiation template.

Thank you for your help,

Václav

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Re: Make MAP use dedicated hardware from behavioral code

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Hi,

 

You can use USE_DSP48 attribute in HDL to force implementation of logic on to DSP.

 

Refer to page-443 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst_v6s6.pdf for details on constraint usage.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
11,896 Views
Registered: ‎09-20-2012

Re: Make MAP use dedicated hardware from behavioral code

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Hi,

 

You can use USE_DSP48 attribute in HDL to force implementation of logic on to DSP.

 

Refer to page-443 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst_v6s6.pdf for details on constraint usage.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

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Visitor
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Registered: ‎02-20-2014

Re: Make MAP use dedicated hardware from behavioral code

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Thank you very much, it works. I added within the entity declaration:

    attribute use_dsp48 : string;
    attribute use_dsp48 of Adder : entity is "yes";

 

The only thing I don't understand is why is the DSP slice implementation slower than the LUT implementation? I thought dedicated hardware would be always faster than general logics.

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Historian
Historian
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Registered: ‎02-25-2008

Re: Make MAP use dedicated hardware from behavioral code

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@vaclav wrote:

 

The only thing I don't understand is why is the DSP slice implementation slower than the LUT implementation? I thought dedicated hardware would be always faster than general logics.


Perhaps it's the routing into the adder that's the slow part. Make sure the adder input is registed.

----------------------------Yes, I do this for a living.
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Visitor
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Registered: ‎02-20-2014

Re: Make MAP use dedicated hardware from behavioral code

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I made the output registered and not the input. I want a single cycle adder, so I can't have both.

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Historian
Historian
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Registered: ‎02-25-2008

Re: Make MAP use dedicated hardware from behavioral code

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@vaclav wrote:

I made the output registered and not the input. I want a single cycle adder, so I can't have both.


remember how the timing analyzer calculates the period. It's from one register's Q output, through whatever logic, to the next register's D input. If there is "stuff" before your inputs hit the adder's inputs, that "stuff" adds to the prop delay.

 

Your choices include pipelining, accepting the reduced operating frequency, and accepting the latency.

----------------------------Yes, I do this for a living.
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