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Explorer
Explorer
8,980 Views
Registered: ‎10-29-2008

Map Error 866 "Not enough valid sites to place the following IOBs"

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I am using ISE 14.2 Embedded Edition with a Spartan-6 150T FG484.

 

My design contains a single MicroBlaze processor.

 

I started with a prototype design from an SP605 board and converted to my real design using the larger device.  I was careful to update all device references to use the larger 150T device.

 

The SP605 uses LVCMOS25 whereas my board with use LVCMOS33.

 

I filled in my UCF file with all my signals, but only some caused errors.

 

Here is the error I get from Map:


INFO:Place:834 - Only a subset of IOs are locked. Out of 92 IOs, 89 are locked
   and 3 are not locked.  The following is the list of components that are not
   locked.
   OA_o_SYS_OK      NOT LOCKED
   OA_o_HP_INHIBIT      NOT LOCKED
   OA_o_ATTENUATION_EN      NOT LOCKED
   Rest of the IOs are LOCKED

ERROR:Place:866 - Not enough valid sites to place the following IOBs:
   IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
   OUTPUT, DRIVE_STR = 12
       OA_o_SYS_OK
       OA_o_HP_INHIBIT
       OA_o_ATTENUATION_EN

   This may be due to either an insufficient number of sites available on the
   device, too many prohibited sites,
   or incompatible I/O Standards locked or range constrained to I/O Banks with
   valid sites.
       This situation could possibly be resolved by one (or all) of the
   following actions:
   a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by
   using LOC or range constraints.
   b) Maximizing available I/O Banks resources for special IOBs by choosing
   lower capacity I/O Banks if possible.
   c) If applicable, decreasing the number of user prohibited sites or using a
   larger device.

And here are the corresponding entries in my UCF file:


NET OA_o_SYS_OK LOC = "B20" | IOSTANDARD = "LVCMOS33";

 

NET OA_o_HP_INHIBIT LOC = "F22" | IOSTANDARD = "LVCMOS33";

NET OA_o_ATTENUATION_EN LOC = "J20" | IOSTANDARD = "LVCMOS33";

You can see that I do in fact have these LOCKED. 

 

And in my MHS file:


 PORT OA_o_ATTENUATION_EN = OA_o_ATTENUATION_EN, DIR = O
 PORT OA_o_HP_INHIBIT = OA_o_HP_INHIBIT, DIR = O
 PORT OA_o_SYS_OK = OA_o_SYS_OK, DIR = O, SIGIS = NONE

I have tried swapping IO pins for SYS_OK from B20 to A20 where A20 is on a pin that does not give errors, but it still says SYS_OK is not LOCKED and gives the exact same error.

 

I even tried removing SYS_OK which was orginally name OK and adding it back in with a new name SYS_OK and still I have get the same error.

 

I have also cleaned design files and rebuilt the design clean.  No luck.

 

I know from reading around that LVCMOS25 is the default so that makes sense as to why if the pins are LOCKED they go to LVCMOS25.  What I don't understand is why are they not LOCKED.

 

Any idea what is going on here?

 

Thanks.

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1 Solution

Accepted Solutions
Explorer
Explorer
6,021 Views
Registered: ‎10-29-2008

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

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It turns out this is a bug in ISE/EDK intergration dealing with contraints.

 

In a related thread I have posted a workaround for this issue I received from a Xilinx Webcase.

 

Workaround on Another Thread

 

 

View solution in original post

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10 Replies
Adventurer
Adventurer
8,969 Views
Registered: ‎02-09-2012

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

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Usually this is a problem of writing. The tools mix up capital and non capital naming. Maybe you succeed in rename the signals to total capital spelling - espacially in the ucf.

 

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Professor
Professor
8,965 Views
Registered: ‎08-14-2007

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

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The attributes listed for the "un-locked" nets are all defaults.  This seems to indicate that

ISE is not actually using your .ucf file.  The first thing I would do is try to intentionally add

a syntax error to the .ucf file to see if it gets flagged as an error.  If not, then try to remove

the .ucf file from the project and add it back in.

 

I have seen cases where a .ucf file is in the project but does not show up in the hierarchy

under the top level instance.  Usually only removing the .ucf from the project and then

adding it back fixes the issue.  Most often the issue happens if you change the top-level

module.

 

-- Gabor

-- Gabor
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Explorer
Explorer
8,961 Views
Registered: ‎10-29-2008

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

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I removed a semicolon on the NET right before the SYS_OK one as follows:

 

NET OA_o_HS_TX LOC = "A20"  | IOSTANDARD = "LVCMOS33"  

NET OA_o_SYS_OK LOC = "B20" | IOSTANDARD = "LVCMOS33";

 

It gave me the following Translate Error:

 

ERROR:ConstraintSystem:300 - In file:
   C:\Projects\Processor\HW/microblaze_pss.n
   cf(54): Syntax error.  Ensure that the previous constraint specification was
   terminated with ';'.

 

So it looks like it is reading my file.  It is just strange that it does not have a problem with the HS_TX or the NET that comes after SYS_OK, just SYS_OK and the other two further down in my file.

 

Any other thoughts? 

 

I will try ALL CAPS next.

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Explorer
Explorer
8,955 Views
Registered: ‎10-29-2008

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

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I tried your suggestion of all caps and got the same result.

 


 

NFO:Place:834 - Only a subset of IOs are locked. Out of 92 IOs, 89 are locked
   and 3 are not locked.  The following is the list of components that are not
   locked.
   SYS_OK      NOT LOCKED
   ATTENUATION_EN      NOT LOCKED
   HP_INHIBIT      NOT LOCKED
   Rest of the IOs are LOCKED

ERROR:Place:866 - Not enough valid sites to place the following IOBs:
   IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
   OUTPUT, DRIVE_STR = 12
       SYS_OK
       ATTENUATION_EN
       HP_INHIBIT

 

 


NET SYS_OK LOC = "B20" | IOSTANDARD = "LVCMOS33";

NET HP_INHIBIT LOC = "F22" | IOSTANDARD = "LVCMOS33";

NET ATTENUATION_EN LOC = "J20" | IOSTANDARD = "LVCMOS33";

 

Note: I am only showing the offending NETs here.  There are a total of 92 and all ther others work fine.

 

Any other suggestions?

 

Thanks.

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Professor
Professor
8,950 Views
Registered: ‎08-14-2007

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

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The only other thing I can suggest is that ISE is using some historical data rather than the

latest code.  You could try to "cleanup project files" from ISE or "clean hardware" from XPS.

 

-- Gabor

-- Gabor
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Explorer
Explorer
8,944 Views
Registered: ‎10-29-2008

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

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Yes that is a good idea, but I already did that.

 

I have my code in SCM so I deleted the old folder, got my code back from SCM (which doesn't contain all the build results) and then did "Cleanup Project Files".

 

I am thinking of moving some things around in the core I am connecting the signals too.

 

Is there and editor I can load the UCF file in that would provide dropdowns?  I have been editing it in the text editor in XPS.

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Explorer
Explorer
8,935 Views
Registered: ‎10-29-2008

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

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My core has several signals on it.

 

Two of the signals giving me trouble are:

ATTENUATION_EN

HP_INHIBIT

 

I decided to swap NET names with two other signals on my core that are not giving me trouble.

OA_o_ST_EN

OA_o_ST_SIG

 

I left my UCF file the same but now I have my core connected as follows:

ATTENUATION_EN = OA_o_ST_EN

HP_INHIBIT = OA_o_ST_SIG

and

OA_o_ST_EN = ATTENUATION_EN

OA_o_ST_SIG = HP_INHIBIT

 

The interesting thing is now I am getting errors about OA_o_ST_EN and OA_o_ST_SIG not being LOCKED.  So it looks like whatever I connect to the ATTENUATION_EN and HP_INHIBIT signals on my core will never be LOCKED no matter what I name them.  And if I put the old NET names on other core signals they work fine.

 

What could cause this?

 

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Professor
Professor
8,931 Views
Registered: ‎08-14-2007

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

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I would start by looking at what the non-working ports might have in common.  And of course

what might be different between these and the working ports.  Did you get any warnings

about the non-working ports when you synthesized the design?  They seem to be inputs

to your core.  Are all of the core inputs exhibiting the problem?  Were these ports added

to your core after the other working ports?  Again there may be some usage of historical

build data causing "new" ports to become disconnected...

 

-- Gabor

-- Gabor
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Explorer
Explorer
8,923 Views
Registered: ‎10-29-2008

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

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I went back to my original SP605 project and tried some things and noticed my LED signals where doing strange things as well.  For example LED<1> was showing LOCKED even though it was not in the UCF file at all.

 

I then looked at my VHDL.  All the signals giving me trouble where also connected to the LED signals inside the core.  When I commented out the assignment of SYS_OK to LED<1> the issue for SYS_OK went away.

 

The final solution was to create a process and s_led signals and assign my SYS_OK and others on each clock thus registering them.  I then did a bulk assignment LED <= s_led; outside the process and everything works now.  See below.

 

-- External Signals

SYS_OK : out std_logic;

ATTENUATION_EN : out std_logic;

HP_INHIBIT : out std_logic;

LED : out std_logic_vector (7 downto 0);

-- Note: Many other signals not show

 

------------------------------------ORIGINAL CODE

LED(0) <= '1';

LED(1) <= SYS_OK;

LED(2) <= s_x_ok;

LED(3) <= s_y_ok;

LED(4) <= ATTENUATION_EN;

LED(5) <= HP_INHIBIT;

LED(6) <= s_z_en;

LED(7) <= s_a_en;

------------------------------------ORIGINAL CODE

 

------------------------------------NEW CODE FIX

 

-- Register

signal s_led : std_logic_vector (7 downto 0) := (others => '0');

 

-- LED Process

LED_REG : process(Bus2IP_Clk) is

begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then

        if Bus2IP_Resetn = '0' then

            s_led <= (others=>'0');

        else

            s_led(0) <= '1';

            s_led(1) <= SYS_OK;

            s_led(2) <= s_x_ok;

            s_led(3) <= s_y_ok;

            s_led(4) <= ATTENUATION_EN;

            s_led(5) <= HP_INHIBIT;

            s_led(6) <= s_x_en;

            s_led(7) <= s_a_en;

        end if;

    end if;

end process LED_REG;

 

LED <= s_led;

        

------------------------------------NEW CODE FIX

 

So it seems having the signals routed out of my core basically under two different names (i.e. SYS_OK and LED<1> for example).  Caused the problem.  It doesn't seem like assigning a control signal to an additional pin to light an LED should cause an issue but it did. 

The fix  was to register the signals and assign the output of the registers to the LED bus which made the problem go away. 

 

The only remaining question is: Is this an ISE/XPS bug or a feature that I just didn't understand well enough?

 

Does a Xilinx Employee know the answer to my last question?

 

Thanks for everyone's help.

 

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Explorer
Explorer
6,022 Views
Registered: ‎10-29-2008

Re: Map Error 866 "Not enough valid sites to place the following IOBs"

Jump to solution

It turns out this is a bug in ISE/EDK intergration dealing with contraints.

 

In a related thread I have posted a workaround for this issue I received from a Xilinx Webcase.

 

Workaround on Another Thread

 

 

View solution in original post

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