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mapedd
Adventurer
Adventurer
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Registered: ‎12-21-2011

Map Error Pack:2529 with IDDR2 on Spartan 6

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Hi folks!

 

After successfully implementing my design on two package versions of the xc6slx150t, time has come to the third one : fgg676.

 

I'm getting seriously weird errors during map process:

 

Started : "Map".
Running map...
Command Line: map -filter "c:/Documents and Settings/mapedd/Pulpit/GIT/INREVIUM_DEV_KIT/iseconfig/filter.filter" -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o m_inrevium_top_map.ncd m_inrevium_top.ngd m_inrevium_top.pcf
Using target part "6slx150tfgg676-3".
Mapping design into LUTs...
WARNING:MapLib:701 - Signal clk_in_p<2> connected to top level port clk_in_p<2>
   has been removed.
WARNING:MapLib:701 - Signal clk_in_n<3> connected to top level port clk_in_n<3>
   has been removed.
WARNING:MapLib:701 - Signal clk_in_p<4> connected to top level port clk_in_p<4>
   has been removed.
WARNING:MapLib:701 - Signal clk_in_n<5> connected to top level port clk_in_n<5>
   has been removed.
WARNING:MapLib:701 - Signal clk_in_p<6> connected to top level port clk_in_p<6>
   has been removed.
WARNING:MapLib:701 - Signal clk_in_n<7> connected to top level port clk_in_n<7>
   has been removed.
Running directed packing...
ERROR:Pack:2529 - The dual data rate register
   "data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[10].inst_ser2par/inst_iddr" failed to join an ILOGIC component as required.
ERROR:Pack:2529 - The dual data rate register
   "data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[9].inst_ser2par/inst_iddr" failed to join an ILOGIC component as required.
ERROR:Pack:2529 - The dual data rate register
   "data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[12].inst_ser2par/inst_iddr" failed to join an ILOGIC component as required.
ERROR:Pack:2529 - The dual data rate register
   "data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[14].inst_ser2par/inst_iddr" failed to join an ILOGIC component as required.
ERROR:Pack:2529 - The dual data rate register
   "data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[8].inst_ser2par/inst_iddr" failed to join an ILOGIC component as required.
ERROR:Pack:2529 - The dual data rate register
   "data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[11].inst_ser2par/inst_iddr" failed to join an ILOGIC component as required.
ERROR:Pack:2529 - The dual data rate register
   "data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[13].inst_ser2par/inst_iddr" failed to join an ILOGIC component as required.
ERROR:Pack:2529 - The dual data rate register
   "data_buffer_inst/data_standarizer/data_rx_inst/gen_ser2par[15].inst_ser2par/inst_iddr" failed to join an ILOGIC component as required.

Mapping completed.
See MAP report file "m_inrevium_top_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   8
Number of warnings :   6

 I've googled around for this error but it was fruitless:(

 

Does any one have some insight what can cause this error to occure?

 

Thanks for any help!

 

i've attached my design for a reference 

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Accepted Solutions
bwade
Scholar
Scholar
10,613 Views
Registered: ‎07-01-2008

I was using an internal tool to trace logic in the NGD. I recommend that you use PlanAhead to examine the netlist connectivity.

View solution in original post

6 Replies
bwade
Scholar
Scholar
8,471 Views
Registered: ‎07-01-2008

For the first error I'm seeing (by tracing logic in NGD file) that the IDDR2 has no pad connectivity. It is driven by an IODELAY and the IODELAY has constants on it's inputs. Is this what you are expecting?

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mapedd
Adventurer
Adventurer
8,465 Views
Registered: ‎12-21-2011

Of course not:)

 

They should be connected to an input port of the device

 

Wrong NET locations in the UCF file may be the problem?

 

Thanks!

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bwade
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Scholar
8,462 Views
Registered: ‎07-01-2008

UCF constraints don't affect the connectivity which is determined upsteam by the synthesis tool.

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mapedd
Adventurer
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8,450 Views
Registered: ‎12-21-2011

ok , so there probably somethings wrong with the connections inside my HDL...

How can i inspect NGD file to find unconnected blocks?

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bwade
Scholar
Scholar
10,614 Views
Registered: ‎07-01-2008

I was using an internal tool to trace logic in the NGD. I recommend that you use PlanAhead to examine the netlist connectivity.

View solution in original post

mapedd
Adventurer
Adventurer
8,434 Views
Registered: ‎12-21-2011

i found the problem, some pins inside the HDL weren't connected, thanks for help!

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