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Explorer
Explorer
9,581 Views
Registered: ‎10-29-2008

Map WARNING:Place:837 - Partially locked IO Bus is found.

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I am using ISE 14.2 Embedded Edition with a Spartan-6 150T FG484.

My design contains a single MicroBlaze processor.

I had a similar problem to this See Thread (Map Error 866 "Not enough valid sites to place the following IOBs")
I that case I found a workaround for the issue.

I now have another set of signals with a similar problem but the workaround does not do the trick.

I orignally had the following in my code which causes warnings and errors.
DBG <= (others=>'0'); -- No Debug items yet, set to zero for now;

I changed to use my register work around (see all code below) and got the exact same errors
For now I just disconnected the DBG bus in XPS so I can continue working.

It really seems like a bug in ISE/XPS that this would happen.  Anyone have any ideas?

 

-- External Signal on MyCore
DBG : out std_logic_vector (15 downto 0);

-- Signal to register Debug Values
signal s_dbg : std_logic_vector (15 downto 0) := (others => '0');

-- Process to Register Debug Values, currently all zeros
DBG_REG : process(Bus2IP_Clk) is
begin
    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
        if Bus2IP_Resetn = '0' then
            s_dbg <= (others=>'0');
        else
            s_dbg <= (others=>'0'); -- No Debug items yet, set to zero for now
        end if;
    end if;
end process DBG_REG;

-- Assignment of registers to external
DBG <= s_dbg;

-- Debug in UCF file
NET MYC_o_DBG[*] IOSTANDARD = "LVCMOS33"; # DB#
NET MYC_o_DBG[0] LOC = "P19";
NET MYC_o_DBG[1] LOC = "R19";
NET MYC_o_DBG[2] LOC = "P22";
NET MYC_o_DBG[3] LOC = "R20";
NET MYC_o_DBG[4] LOC = "T20";
NET MYC_o_DBG[5] LOC = "T22";
NET MYC_o_DBG[6] LOC = "U20";
NET MYC_o_DBG[7] LOC = "U22";
NET MYC_o_DBG[8] LOC = "T19";
NET MYC_o_DBG[9] LOC = "V22";
NET MYC_o_DBG[10] LOC = "W22";
NET MYC_o_DBG[11] LOC = "Y22";
NET MYC_o_DBG[12] LOC = "T18";
NET MYC_o_DBG[13] LOC = "T17";
NET MYC_o_DBG[14] LOC = "W18";
NET MYC_o_DBG[15] LOC = "V17";

-- Top level port in MHS file
PORT MYC_o_DBG = MYC_o_DBG, DIR = O, VEC = [15:0]

-- Debug port connected to MyCore in MHS file
BEGIN MyCore
... Other stuff in here
PORT DBG = MYC_o_DBG
END

-- Map Warnings and Errors
-- Note: It is saying that MYC_o_DBG<15> is LOCKED but not the others.  That does not make sense to me at all.
--       This is similar to another problem I had with some LED signals, but that was resovled by registering their outputs
--       See "Comp: MYC_o_DBG<15>   IOSTANDARD = LVCMOS33" line below

Phase 2.7  Design Feasibility Check
WARNING:Place:837 - Partially locked IO Bus is found.
    Following components of the bus are not locked:
        Comp: MYC_o_DBG<14>
        Comp: MYC_o_DBG<13>
        Comp: MYC_o_DBG<12>
        Comp: MYC_o_DBG<11>
        Comp: MYC_o_DBG<10>
        Comp: MYC_o_DBG<9>
        Comp: MYC_o_DBG<8>
        Comp: MYC_o_DBG<7>
        Comp: MYC_o_DBG<6>
        Comp: MYC_o_DBG<5>
        Comp: MYC_o_DBG<4>
        Comp: MYC_o_DBG<3>
        Comp: MYC_o_DBG<2>
        Comp: MYC_o_DBG<1>
        Comp: MYC_o_DBG<0>

WARNING:Place:838 - An IO Bus with more than one IO standard is found.
   Components associated with this bus are as follows:
        Comp: MYC_o_DBG<0>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<1>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<2>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<3>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<4>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<5>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<6>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<7>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<8>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<9>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<10>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<11>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<12>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<13>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<14>   IOSTANDARD = LVCMOS25
        Comp: MYC_o_DBG<15>   IOSTANDARD = LVCMOS33  -- Why is this one different?


INFO:Place:834 - Only a subset of IOs are locked. Out of 124 IOs, 109 are locked
   and 15 are not locked.  The following is the list of components that are not
   locked.
   MYC_o_DBG<0>      NOT LOCKED
   MYC_o_DBG<1>      NOT LOCKED
   MYC_o_DBG<2>      NOT LOCKED
   MYC_o_DBG<3>      NOT LOCKED
   MYC_o_DBG<4>      NOT LOCKED
   MYC_o_DBG<5>      NOT LOCKED
   MYC_o_DBG<6>      NOT LOCKED
   MYC_o_DBG<7>      NOT LOCKED
   MYC_o_DBG<8>      NOT LOCKED
   MYC_o_DBG<9>      NOT LOCKED
   MYC_o_DBG<10>      NOT LOCKED
   MYC_o_DBG<11>      NOT LOCKED
   MYC_o_DBG<12>      NOT LOCKED
   MYC_o_DBG<13>      NOT LOCKED
   MYC_o_DBG<14>      NOT LOCKED
   Rest of the IOs are LOCKED

ERROR:Place:866 - Not enough valid sites to place the following IOBs:
   IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
   OUTPUT, DRIVE_STR = 12
       MYC_o_DBG<0>
       MYC_o_DBG<1>
       MYC_o_DBG<2>
       MYC_o_DBG<3>
       MYC_o_DBG<4>
       MYC_o_DBG<5>
       MYC_o_DBG<6>
       MYC_o_DBG<7>
       MYC_o_DBG<8>
       MYC_o_DBG<9>
       MYC_o_DBG<10>
       MYC_o_DBG<11>
       MYC_o_DBG<12>
       MYC_o_DBG<13>
       MYC_o_DBG<14>

   This may be due to either an insufficient number of sites available on the
   device, too many prohibited sites,
   or incompatible I/O Standards locked or range constrained to I/O Banks with
   valid sites.
       This situation could possibly be resolved by one (or all) of the
   following actions:
   a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by
   using LOC or range constraints.
   b) Maximizing available I/O Banks resources for special IOBs by choosing
   lower capacity I/O Banks if possible.
   c) If applicable, decreasing the number of user prohibited sites or using a
   larger device.

Thanks for your help.

 

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1 Solution

Accepted Solutions
Explorer
Explorer
7,254 Views
Registered: ‎10-29-2008

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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I tried Bob's suggestion and it did not work for me.  The tools just regenerated the original mig.ucf file.

 

Here is my project in "Project Navigator".  It includes the "override" UCF which I will talk about below.

 

ProjectParts.png

 

I finally got a response from Xilinx on my Web Case.

 

Basically the problem I am having is a bug in ISE/EDK.  A Xilinx representative stated that there is a bug in ISE/EDK integration in handling constraints automatically.  They plan to fix it in Vivado, but for ISE/EDK I am forced to use a workaround. 

 

The workaround is to take the UCF file in the XPS project and make an exact copy of it will a different filename.  Then add this new "override" file to the top level project as I have done above.

 

I am told I will just have to keep the two in sync manually. 

 

This workaround did fix the issue but caused a bunch of warnings to popup because the constraints were being overridden.  Never the less, I am able to continue with my project building without error and functioning correctly now.

 

Thanks for everyone's help.  Hopefully others will find this workaround useful.

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11 Replies
Xilinx Employee
Xilinx Employee
9,574 Views
Registered: ‎07-01-2008

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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You need to be very careful when using wildcard constraints like that. It can match an internal signal and then propagate to an unintended IO signal overriding constraints that were applied directly there. I wrote the following Answer Record about this some time ago:

http://www.xilinx.com/support/answers/33927.htm

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Professor
Professor
9,563 Views
Registered: ‎08-14-2007

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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This looks like the same bug you discovered in your other thread.  What happens is that

you have multiple pins essentially driven from the same net.  In the original you had

LED pins sharing a net with another pin.  Here you have multiple debug pins sharing

the ground net.  What appears to be happening is that XPS is combining the nets before

translation, meaning that some net names will no longer match the constraints because

they were merged with an equivalent net.

 

This should not happen with top level ports, of course.  So it appears to be a bug,

and you'd probably be best to open a webcase for it.

 

-- Gabor

-- Gabor
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Explorer
Explorer
9,553 Views
Registered: ‎10-29-2008

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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bwade,

 

So are you suggesting I change

 

NET MYC_o_DBG[*] IOSTANDARD = "LVCMOS33"; # DB#
NET MYC_o_DBG[0] LOC = "P19";
NET MYC_o_DBG[1] LOC = "R19";
NET MYC_o_DBG[2] LOC = "P22";

...

 

to

 

NET MYC_o_DBG[0] LOC = "P19" | IOSTANDARD = "LVCMOS33";
NET MYC_o_DBG[1] LOC = "R19" | IOSTANDARD = "LVCMOS33";
NET MYC_o_DBG[2] LOC = "P22" | IOSTANDARD = "LVCMOS33";

...

 

and so on to replace all uses of [*]?

 

Thanks.

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Explorer
Explorer
9,552 Views
Registered: ‎10-29-2008

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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Gabor,

 

Yes, it does look like the same issue.

 

Your summarization seems to get to the heart of the problem.

 

If getting rid of [*] like I think bwade is suggesting doesn't fix it I will open a Web Case.

 

I am using ISE/XPS 14.2. 

 

What version of the tools are you using?

 

Have you ever seen this issue in your work?

 

Thanks.

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Explorer
Explorer
9,540 Views
Registered: ‎10-29-2008

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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Ok, I tried removing all [*] references in my UCF and replacing with per signal contraints. 

 

There are now *NO* wildcards left in my UCF file.

 

The result was exactly the same.  I got the identical errors that I did orignally.

 

As usual I did "Clean Project Files" before doing a complete rebuild.

 

Seems like this is and ISE/XPS bug for sure now.

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Professor
Professor
9,516 Views
Registered: ‎08-14-2007

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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@digitalone wrote:

Gabor,

 

Yes, it does look like the same issue.

 

Your summarization seems to get to the heart of the problem.

 

If getting rid of [*] like I think bwade is suggesting doesn't fix it I will open a Web Case.

 

I am using ISE/XPS 14.2. 

 

What version of the tools are you using?

 

Have you ever seen this issue in your work?

 

Thanks.


I use a lot of different versions of tools, but have not seen this specific bug.  On the other

hand I have not yet used 14.2 (my most current project uses 13.4) and the last project I

used XPS with was in version 11.5

 

Even then I've never used XPS as the top level - I always imported the embedded processor

into an ISE project, so it's not clear whether this is a new bug.

 

That being said, the reason I thought of the net merging is that newer versions of XST
have a related bug when reporting multi-source errors.  Often the signal named in the

error is not actually the signal with the multiple drivers, but another signal that was

assigned with the multiple-driven value.

 

-- Gabor

 

-- Gabor
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Explorer
Explorer
9,499 Views
Registered: ‎10-29-2008

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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I was looking thru the mig.ucf that is generated by the MCB DDR3 controller core.

 

I noticed "CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3"  Which has the voltage at 2.5

 

I also noticed these in the file as well.

NET  "c3_sys_clk_p"                                IOSTANDARD = LVDS_25 ;

NET  "c3_sys_clk_n"                                IOSTANDARD = LVDS_25 ;

NET  "c3_sys_rst_i"                                IOSTANDARD = LVCMOS15 ;

NET  "c3_sys_clk_n"                              LOC = "U12" ;

NET  "c3_sys_clk_p"                              LOC = "T12" ;

NET  "c3_sys_rst_i"                              LOC = "W12" ;

 

They are not in the MHS file so I don't know what they are used for.  I actually need to use the LOCed pins listed above in my design.

 

I tried changing CONFIG VCCAUX=3.3 and removing all the "c3_sys_*" signals from mig.ucf.  When I when to rebuilt the design it was changed back to the previous values by the tools.  I found out that running Design Rule Check was enough to regenerate mig.ucf and overwrite any changes I made.

 

How to I deal with this?  How can I force the 3.3V and remove the "c3_sys_*" signals?

 

Thanks.

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Explorer
Explorer
9,491 Views
Registered: ‎10-29-2008

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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I also tried putting the CONFIG VCCAUX=3.3 at the top of my user constraint file and got the following warning during translate.

 

WARNING:NgdBuild:1012 - The constraint <CONFIG VCCAUX = "3.3"> is overridden on

   the design object microblaze_pss_top by the constraint <CONFIG VCCAUX =

   "2.5">.

 

I finally resorted to a total hack.  I ran a renaming script over and over during the build and when it got to translate it printed

 

WARNING:NgdBuild:1012 - The constraint <CONFIG VCCAUX = "3.3"> is overridden on

   the design object microblaze_pss_top by the constraint <CONFIG VCCAUX =

   "3.3">.

 

And it ended up completing Map and the rest of the build with zero errors.

 

It seems like if I could get this value set to 3.3 I would be good. 

 

Any ideas on how/where I can set CONFIG VCCAUX=3.3 so that it won't be overriden by the mig.ucf?

 

Thanks.

 

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Instructor
Instructor
9,488 Views
Registered: ‎07-21-2009

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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Any ideas on how/where I can set CONFIG VCCAUX=3.3 so that it won't be overriden by the mig.ucf?

 

Copy the stuff you need from the MIG-generated .UCF to your main project .UCF, and rename the MIG-generated .UCF with some harmless filetype extension.

 

This may not be the "party line" answer, but I make a considerable number of modifications to customise the MIG-generated source code.  I preserve these changes by copying the modified source code files to the main project source code folder.  The memory controller appears in the project hierarchy pane (in ISE) as a normal module in the design, and not as a core.

 

-- Bob Elkind

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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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Professor
Professor
4,348 Views
Registered: ‎08-14-2007

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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As I understand the problem, this is an XPS top-level project, not ISE.  In ISE, a MIG core would

not update its .ucf file unless you re-customized it on purpose.

 

If Bob's suggestion doesn't work you may want to start a new thread for this issue in the

Embedded forums.  My own limited experience with XPS has always been projects where

the top level was ISE and the CPU was included in the ISE project.  I find that this method

gives you a lot more control over the back-end processing.

 

-- Gabor

-- Gabor
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Explorer
Explorer
7,255 Views
Registered: ‎10-29-2008

Re: Map WARNING:Place:837 - Partially locked IO Bus is found.

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I tried Bob's suggestion and it did not work for me.  The tools just regenerated the original mig.ucf file.

 

Here is my project in "Project Navigator".  It includes the "override" UCF which I will talk about below.

 

ProjectParts.png

 

I finally got a response from Xilinx on my Web Case.

 

Basically the problem I am having is a bug in ISE/EDK.  A Xilinx representative stated that there is a bug in ISE/EDK integration in handling constraints automatically.  They plan to fix it in Vivado, but for ISE/EDK I am forced to use a workaround. 

 

The workaround is to take the UCF file in the XPS project and make an exact copy of it will a different filename.  Then add this new "override" file to the top level project as I have done above.

 

I am told I will just have to keep the two in sync manually. 

 

This workaround did fix the issue but caused a bunch of warnings to popup because the constraints were being overridden.  Never the less, I am able to continue with my project building without error and functioning correctly now.

 

Thanks for everyone's help.  Hopefully others will find this workaround useful.

View solution in original post