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Observer harisankar98
Registered: ‎09-23-2011

Map error : not enough valid sites to place the following IOBs


following are the details of the design:


Spartan LX150T fpga,

xilinx ise 12.1


I am doing synthesis with


ERROR:Place:866 - Not enough valid sites to place the following IOBs:
   IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = BIDIR, DRIVE_STR = 12

   This may be due to either an insufficient number of sites available on the device, too many prohibited sites,
   or incompatible I/O Standards locked or range constrained to I/O Banks with valid sites.
       This situation could possibly be resolved by one (or all) of the following actions:
   a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by using LOC or range constraints.
   b) Maximizing available I/O Banks resources for special IOBs by choosing lower capacity I/O Banks if possible.
   c) If applicable, decreasing the number of user prohibited sites or using a larger device.



along with that i am getting the following errors also. please check the attached log file.


ERROR:Place:382 - The placer was unable to find a feasible solution for the IOBs in your design. This is possibly due to
   SelectIO banking constraints.

   Each Group of a specific Standard is listed.
   Standard SSTL18_II (Vref=0.90 Vcco=1.80 Terminate=none) 82 IOs, 82 locked.
     (4-Inputs, 46-Outputs, 32-Bidirectional)
   Standard LVCMOS25 (Vref=NR Vcco=2.50 Terminate=none) 9 IOs, 5 locked.
     (1-Inputs, 4-Outputs, 4-Bidirectional)
   Standard LVCMOS33 (Vref=NR Vcco=3.30 Terminate=none) 83 IOs, 83 locked.
     (7-Inputs, 60-Outputs, 16-Bidirectional)
   Standard LVDS_25 (Vref=NR Vcco=2.50 Terminate=none) 282 IOs, 282 locked.
     (86-Inputs, 196-Outputs, 0-Bidirectional)
   Standard DIFF_SSTL18_II (Vref=NR Vcco=1.80 Terminate=none) 12 IOs, 12 locked.
     (0-Inputs, 4-Outputs, 8-Bidirectional)


ERROR:Place:418 - Failed to execute IOB Placement
Phase 4.2  Initial Placement for Architecture Specific Features (Checksum:e627d965) REAL time: 3 mins 9 secs

Total REAL time to Placer completion: 3 mins 9 secs
Total CPU  time to Placer completion: 2 mins 30 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.



Please help me on this

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7 Replies
Registered: ‎04-09-2008

Re: Map error : not enough valid sites to place the following IOBs

You need to look at the number of IO banks and number of IO per bank available.  Each bank is going to be powered using a certain Vcco voltage, and possibly Vref voltages or reference termination resistors.  That particular configuration of the bank determines the IO standards which will be supported within that bank.


For instance, suppose your FPGA has 160 GPIO in 4 different banks.  You want to use 1.8V and 2.5V logic simultaneously.  As soon as a single 1.8V IO pin is located in a particular bank, the other 39 pins in that bank can no longer be used for your 2.5V logic.


Look at the Spartan user guides for more information about your particular part and IO standards.  You might need a bigger chip with more IO banks.

0 Kudos
Registered: ‎07-21-2009

Re: Map error : not enough valid sites to place the following IOBs

MIG (Spartan-6) routinely places the (default LVCMOS25) clock inputs in the same IO bank as the memory interface signals, which is a conflict for DDR2 and DDR3 applications.  If this is the case, you need to manually configure the primary clock input for your MIG-based design.


From a previous MIG forum thread:


If you are targeting DDR2 or DDR3, and not DDR 1, then VCCO for the MCB's IO BANK must not be 2.5V.  Any IOs inferred for the same IO BANK must either be moved to another bank, or re-defined to a compatible IOSTANDARD.


So...  what IOs do you have assigned to bank 1 which are not SSTL18 or SSTL15?  If it's the clock input instantiated by the MIG output files, then you need to manually edit your .UCF to correct the problem.


For example, here are a few lines from the .UCF file generated by MIG (3.61):


NET  "c1_sys_clk"      IOSTANDARD = LVCMOS25;
NET  "c1_sys_rst_n"    IOSTANDARD = LVCMOS18;
NET  "c1_sys_clk"      LOC = "D9" ;
NET  "c1_sys_rst_n"    LOC = "G9" ;

These represent nothing more than boilerplate assumptions made by MIG.  Just over-write them with your preference for source clock input and reset input.  You may source your MCB reset from inside the FPGA, but that's not one of the customisation options in MIG 3.61 or earlier.


By the way, MIG output also defaults to a 1x memory clock for the source clock.  For example, most designers do not want to provide a 333MHz clock on the circuit board connected to their FPGA.  You will also need to customise the default MIG output to instantiate (for example) a 33MHz LVCMOS33 clock input on bank 0 rather than a 333MHz LVCMOS25 clock input on bank 1 (where it will provoke the error message you listed).


Also:  UCF file - VCCAUX defaults to 2.5V, which may be incorrect for your design.


The bottom line is that MIG does not generate final, unalterable code for your design.  You need to customise the MIG instantiation to fit your design.  Many of the simple customisations can be done from the wrapper level and out (as of MIG 3.61).  Some customisations (for example, generating multiple fabric clocks from the MCB's PLL) require editing the underlying MIG-generated source code files (down to infrastructure).


-- Bob Elkind

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Observer harisankar98
Registered: ‎09-23-2011

Re: Map error : not enough valid sites to place the following IOBs

Thanks eteam00 and pcurt,


here is the IOSTANDARDS i am using for each bank:-


Bank 0 - LVDS_25

Bank 1 - LVDS_25 (input) / LVCMOS25

Bank 2 - LVDS_25

Bank 3 - LVCMOS33

Bank 4 - MCB (SSTL18_II)

Bank 5 - MCB (SSTL18_II)


Also please have a look at the following points:-


1. I dont see mixed usage of IO standards in same bank. LVCMOS25 is used for 5 signals, here are the pins used for them:-

a) Y24, b)Y25, c)AE25, d)AE26, e)AG26   - all of them in Bank 1, remaining IOs in Bank1 are used as LVDS_25


2. I am using two MCBs, one in Bank4 and second one in Bank5 , I am not using any other IOSTANDARD in those banks


3.  VCCAUX i have configured as 3.3V, thts wat i am using


4. I have edited the MIG output files as per thread created by eteam00 (changed FBDIV setting etc.) so that the input frequency of clocks to MCB is much lower (100 MHz in my case)


5. for the two MCBs, the sys_clks are provided from Bank3 (LVCMOS33)  will that be an issue, is there anything like sys_clk should come the same bank itself?


6. its saying "
ERROR:Place:866 - Not enough valid sites to place the following IOBs:
   IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = BIDIR, DRIVE_STR = 12
       IO_x "  

 But I dont have any input or output of LVCMOS25 with the name IO or IO_x .  


7. i hav set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1, and hence i am getting the list of IOs which are not locked, those are :- IO_x_x_x




 I dont have any input/output of that name in my toplevel.v or .ucf mentioned. Then why are these coming!!!..

also it gives the message "INFO:Place:834 - Only a subset of IOs are locked. Out of 468 IOs, 464 are locked
   and 4 are not locked.  The following is the list of components that are not
   locked."  before giving the lost of IOs which are not locked.


Please help me..

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Registered: ‎04-03-2013

Re: Map error : not enough valid sites to place the following IOBs

I have exactly the same problem. Is there anyone who has a solution for this error?


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Xilinx Employee
Xilinx Employee
Registered: ‎07-16-2008

Re: Map error : not enough valid sites to place the following IOBs

My guess is that there're some instantiated IO buffers (IBUF, OBUF etc) in submodule. However, the associated submodule ports are not connected to top-level. That's why you see name like IO_x, which is created automatically by tool, since IO buffer is inserted here.


These ports will use the IOSTANDARD specified in instantiation. In this case, it looks to be LVCMOS25. Check whether there're any conflicts.

Don't forget to reply, kudo, and accept as solution.
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Visitor warloc
Registered: ‎05-02-2017

Re: Map error : not enough valid sites to place the following IOBs

I run into the same problem and got stuck for server hours,eventurally found there is a misspell name in the memory ipcore instantiation(mcb3_zio--zio,mcb3_rzq---rzq,it seems that the raq and zio pin can be placed in other banks,so the "view HDL instantiation template" command will not just copy the port name).
The "IO IO_x_x IO_x" iOs seems to be signals that are optimised after synthesize, you can change the synthersize opition "-keep_hierarchy" to yes to keep the corrsponding singnal name after synthesize,then run map again,you should get the right signal name.
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Observer shivaji.m
Registered: ‎08-23-2015

Re: Map error : not enough valid sites to place the following IOBs

By enabling synth property -keep_hierarchy helps to see which are the signals creating this issue. Info: My project has EDK with MicroBlaze, I have multiple GPIO peripherals exported i/o pins as per my requirement, by default tool adding bidirectional buffer on each of them. Because of EDK generating NGC and handing it to ISE those buffers are left as it is. while you're using that netlist instance, i've observed that if you hooked up even floating net to this instance, strangely synth tool with the default setting not optimizing those IO buffers, so either try synth optimization settings or identify those floating nets and remove. 



Shivaji M

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