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930 Views
Registered: ‎10-16-2019

Map fails but map report has no error messages

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I am running ISE 14.7 using a supported Spartan 6 part. Synthesis and Translation succeed. Map fails yet there are no error messages onthe console or in the map report. I don't know what to do to fix it because the tool is not giving me any error messages.

 

Below are the console messages

 

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -a -uc src/toplevel_locked.ucf -p xc6slx4-cpg196-2 toplevel.ngc toplevel.ngd

Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -a -uc src/toplevel_locked.ucf -p
xc6slx4-cpg196-2 toplevel.ngc toplevel.ngd

Reading NGO file "C:/Xilinx_projects/led_controller_01/toplevel.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "src/toplevel_locked.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0

Writing NGD file "toplevel.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec

Writing NGDBUILD log file "toplevel.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc6slx4-cpg196-2 -w -logic_opt on -ol high -t 1 -xt 0 -r 4 -global_opt area -equivalent_register_removal on -mt off -detail -ir off -pr b -lc auto -power off -o toplevel_map.ncd toplevel.ngd toplevel.pcf
Using target part "6slx4cpg196-2".
Running global optimization...
Mapping design into LUTs...
Running directed packing...

Process "Map" failed

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720 Views
Registered: ‎10-16-2019

Hi All following this thread,

I uninstalled the tool and then re-installed it and the problem is solved. I now get a successful process all the way to generating a programming file.

Regards,

Robin

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syedz
Moderator
Moderator
922 Views
Registered: ‎01-16-2013

robin_bordow@yahoo.com 

 

Can you try after clearing the temp files? Project > Cleanup Project Files.. Also share the MAP file and MRP file which should be present in ISE project directory. 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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ghasemi_r
Explorer
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917 Views
Registered: ‎05-07-2018

Hi

make sure about the correctness of the UCF file

and regenerate your project and create special place for your file and then attach files to the new project. 

I think software has some confusion. 

 

 

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Registered: ‎10-16-2019

I did the cleanup as you suggested but no change in the behavior. Below are the .map and .mrp files

 

here is .map file

Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'toplevel'

Design Information
------------------
Command Line : map -intstyle ise -p xc6slx4-cpg196-2 -w -logic_opt on -ol high
-xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -detail
-ir off -pr b -lc auto -power off -o toplevel_map.ncd toplevel.ngd toplevel.pcf
Target Device : xc6slx4
Target Package : cpg196
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Oct 30 01:25:43 2019

Mapping design into LUTs...
Running directed packing...

 

here is .mrp file

elease 14.7 Map P.20131013 (nt64)
Xilinx Mapping Report File for Design 'toplevel'

Design Information
------------------
Command Line : map -intstyle ise -p xc6slx4-cpg196-2 -w -logic_opt on -ol high
-xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -detail
-ir off -pr b -lc auto -power off -o toplevel_map.ncd toplevel.ngd toplevel.pcf
Target Device : xc6slx4
Target Package : cpg196
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Oct 30 01:25:43 2019

 

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906 Views
Registered: ‎10-16-2019

I completely created a new project in a new directory. The .UCF file appears to be fine. I get the same problem Map fails but there are no error messages

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syedz
Moderator
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Registered: ‎01-16-2013

robin_bordow@yahoo.com 

 

Can you share the archive project of ISE to test this at our end? Project --> Archive

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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892 Views
Registered: ‎10-16-2019

I have commented out all the unused pins and constraints so the project is minimal. Attached is the archived project

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ghasemi_r
Explorer
Explorer
884 Views
Registered: ‎05-07-2018

I implement your project and there is 4 error

I am not sure about your FPGA number but I think you choose the wrong pin for clocks

3.PNG
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syedz
Moderator
Moderator
883 Views
Registered: ‎01-16-2013

robin_bordow@yahoo.com 

 

Attached is the log file. I used ISE 14.7 on linux machine. Are you using supported OS with ISE? 

https://www.xilinx.com/support/answers/18419.html 

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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794 Views
Registered: ‎10-16-2019

Hi Syed,

Thanks for your help so far. I am using a Windows 7 OS. In order to simplify this as much as possible so as to just get to the bottom of why Map is failing, I stripped everything out of the design so that that it is just basically one flipflop. There is a data_in, a clock_in, and a data_out signal. I have attached the new archive. It seems like when you tried it on your system, the errors you got were placement errors, indicating you successfully got through the Map process.

Now that my design is as simple a test case as is humanly possible, and I am still getting a Map failure, I'm hoping you can help me figure out why.

Thanks Again, Robin

 

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721 Views
Registered: ‎10-16-2019

Hi All following this thread,

I uninstalled the tool and then re-installed it and the problem is solved. I now get a successful process all the way to generating a programming file.

Regards,

Robin

View solution in original post

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