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bluez
Visitor
Visitor
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Registered: ‎04-24-2021

Map logic only to SLICEL and not SLICEM in 7 Series FPGA

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Hi,

Is there a way to make sure that a logic block ends up in SLICEL and not SLICEM in a 7 Series FPGA (specifically, in ZYNQ7020)? I am only using combinatorial logic.

Thanks!

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hongh
Moderator
Moderator
621 Views
Registered: ‎11-04-2010

Tool will decide whether to place the combinatorial logic into SLICEL and not SLICEM.

I don't think there is a switch to intervene directly. If you are worried about the shortage of SLICEM, I believe the logic has to use SLICEM will have higher priority for SLICEM.

If you insist on only using SLICEL for combinatorial logic, you can try to create a pblock only contains SLICEL for these logic.

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hongh
Moderator
Moderator
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Registered: ‎11-04-2010

Tool will decide whether to place the combinatorial logic into SLICEL and not SLICEM.

I don't think there is a switch to intervene directly. If you are worried about the shortage of SLICEM, I believe the logic has to use SLICEM will have higher priority for SLICEM.

If you insist on only using SLICEL for combinatorial logic, you can try to create a pblock only contains SLICEL for these logic.

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-------------------------------------------------------------------------

View solution in original post

bluez
Visitor
Visitor
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Registered: ‎04-24-2021

Thanks hongh! I'll try to create a pblock then.

Although, can you give me an example of how I can create such a pblock? How do I list out so many SLICEL locations?

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hongh
Moderator
Moderator
536 Views
Registered: ‎11-04-2010

Hi, @bluez ,

You are welcome. Please try the below command to remove SLICEM from the pblock area:

Ex: 

create_pblock pblock_1
resize_pblock pblock_1 -add {SLICE_X2Y100:SLICE_X11Y124 RAMB18_X0Y40:RAMB18_X0Y49 RAMB36_X0Y20:RAMB36_X0Y24}
add_cells_to_pblock pblock_1 [get_cells [list arnd4]] -clear_locs

resize_pblock pblock_1 -remove [get_sites -filter {SITE_TYPE == SLICEM} -of [get_pblocks pblock_1 ] ]

Assuming the pblock name is pblock_1

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bluez
Visitor
Visitor
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Registered: ‎04-24-2021

Thanks for the example! I did try it out and I think it should work but somehow it doesn't. I mean the pblock is correctly defined, and my cells are assigned this pblock on their PBLOCK property, but the placer still places them in SLICEM's outside this pblock as it did before.

There does not seem to be anything in my design that would require a SLICEM, or anything that indicated that it would not fit in my defined pblock (it's just some LUT6_2's and FDRE FF's). Although I do use RLOC constraints for these cells within the HDL, just to keep them together in a single column of slices (Removing RLOC does not solve the issue either). What do you think the problem could be? 

I am stuck at my work because of this, any help would be highly appreciated!

Note: I am using Vivado 2020.2

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hongh
Moderator
Moderator
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Registered: ‎11-04-2010

Please try to disable IS_SOFT property of Pblock in Vivado 2020.2:

Ex: set_property IS_SOFT 0 [get_pblocks pblock_XX ]

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bluez
Visitor
Visitor
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Registered: ‎04-24-2021

It worked! Thanks a bunch!

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jsobas
Observer
Observer
270 Views
Registered: ‎11-02-2020

Hey,

In the same FPGA architecture I realize 5 Ring Oscillator. For this I use "generate" function.

When I run implementation, Vivado optimize this step puting further Ring Oscillator in SLICEL (picture 1) and other in SLICEM (picture 2).

I don't understand why vivado one time implement the Ring Ocillator in SLICEL and other time in SLICEM ?

I use only combinatorial logic to build Ring Oscillator...so normally Vivado should use SLICEL no ?

I try the following command in my xdc file, but doesn't work (see Errors messages in picture 3):

create_pblock pblock_1
set_property IS_SOFT FALSE [get_pblocks pblock_1]
resize_pblock pblock_1 -add {SLICE_X15Y173:SLICE_X15Y178}
add_cells_to_pblock pblock_1 [get_cells [list RO_BENCH]] -clear_locs
resize_pblock pblock_1 -remove [get_sites -filter {SITE_TYPE == SLICEM} -of [get_pblocks pblock_1 ] ]

In the picture 4 you will find the Netlist.

If anyone can help me I would be very grateful

Note : I use XCZU3EG FPGA and vivado  2020.2

 

 

 

 

picture 1.PNG
picture 2.PNG
picture 3.PNG
picture 4.PNG
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barriet
Xilinx Employee
Xilinx Employee
267 Views
Registered: ‎08-13-2007

@jsobasA SLICEM is a superset of the SLICEL - in addition to combinatorial logic, it can also do shift registers and distributed memory.
See https://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf chapter 2.

I don't see why the tools wouldn't use the SLICEM if it was available unless you told it not too.

Cheers,
bt

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jsobas
Observer
Observer
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Registered: ‎11-02-2020

@barriet  I understand that SLICEM provides a combinatorial logic function. But the ring oscillator needs to measure the propagation time of a LUT. For that I have to make sure that for the same boolean function the implementation is identical to be sure to measure the same thing.
What I don't understand in the DataSheet: If the shift registers and distributed memory features are not used in the SLICEM, the input signals will be propagated in the same internal architecture (at the transistor scale) as in a SLICEL?
Is it possible to know the internal architecture of the LUTs at transistor scale?

Thanks

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barriet
Xilinx Employee
Xilinx Employee
217 Views
Registered: ‎08-13-2007

@jsobasThe user guide I referenced is the public documentation here - transistor details are not available.

That said:
-you might be able to glean some details from the timing report
-there are likely useful details in the public patents but that covers 35+ years and thousands of publications - and no correlation to device family
-there's literally of dozens of papers and even forum threads here about building fabric-based ring oscillators or RO PUFs
that said, the silicon and the tools are NOT designed for this asynchronous methodology and you'll be swimming upstream some of the time. This is not an officially supported methodology and it poses quite a number of challenges - including tools/methodology, repeatability, PVT effects, placement, routing, etc.

Cheers,
bt