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Contributor
Contributor
7,234 Views
Registered: ‎10-21-2012

MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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Hi forum,

 

   I am having an odd error in MAP. I have a xilinx IP core divider and it seems to be complaining about it during MAP. I am running on ISE 13.2 with an ML507 board. The warrning I get for this IP Divider is:

 

NgdBuild:483 - Attribute "INIT" on "conv_2d_0/conv_2d_0/USER_LOGIC_I/foo/conv2ddp/divider_inst/blk00000003/sig0000010e" is on the wrong type of object.  Please see the Constraints Guide for more information on this attribute.

 

for MAP I get:

 

A Bunch of These types two main types of errors:

 

---------------------------

ERROR:MapLib:979 - LUT2 symbol
   "conv_2d_0/conv_2d_0/USER_LOGIC_I/foo/conv2ddp/divider_inst/blk00000003/blk00

000607" (output
   signal=conv_2d_0/conv_2d_0/USER_LOGIC_I/foo/conv2ddp/divider_inst/blk00000003
   /sig0000006b) has input signal
   "conv_2d_0/conv_2d_0/USER_LOGIC_I/foo/conv2ddp/divider_inst/dividend<22>"
   which will be trimmed. See Section 5 of the Map Report File for details about
   why the input signal will become undriven.

---------------------------

ERROR:MapLib:978 - LUT2 symbol
   "conv_2d_0/conv_2d_0/USER_LOGIC_I/foo/conv2ddp/divider_inst/blk00000003/blk00

00061b" (output
   signal=conv_2d_0/conv_2d_0/USER_LOGIC_I/foo/conv2ddp/divider_inst/blk00000003
   /sig0000006e) has an equation that uses input pin I1, which no longer has a
   connected signal. Please ensure that all the pins used in the equation for
   this LUT have signals that are not trimmed (see Section 5 of the Map Report
   File for details on which signals were trimmed).

---------------------------

 

I saw the following Posts and AR records:

 

http://www.xilinx.com/support/answers/30477.htm

http://www.xilinx.com/support/answers/35431.html

 

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/ERROR-MapLib-979-LUT2-symbol-error-help-plz-it-is-urgent/td-p/39130

 

But these didn't really help me. Has anyone seen this before?

 

Thanks

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1 Solution

Accepted Solutions
Scholar austin
Scholar
9,428 Views
Registered: ‎02-27-2008

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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File a webcase, and report it as a bug.

 

If you do not have access to webcase, let me know, so I may forward it.

 

We are working on a way to report bugs for anyone/everyone.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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12 Replies
Scholar austin
Scholar
7,225 Views
Registered: ‎02-27-2008

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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How is the LUT being used?

 

LUTRAM, SRL, or just logic?

 

It says there is a missing input signasl, and logic is being trimmed (thrown out).  Perhaps the problem starts with the missing input?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Contributor
Contributor
7,218 Views
Registered: ‎10-21-2012

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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That is a good question. This is part of a Xilinx IP Divider, I am only using the NGC file that is created from Core Generator.
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Xilinx Employee
Xilinx Employee
7,213 Views
Registered: ‎07-01-2008

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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Trimming can occur for a number of reasons, some design issues, some sw bugs. I wrote this AR that attempts to cover all possibilities:

http://www.xilinx.com/support/answers/23990.htm

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Community Manager
Community Manager
7,189 Views
Registered: ‎06-14-2012

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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I would suggest to try a latest version of tools if possible. There might be some issues that could have been fixed in latest versions.

 

Can you try map -ignore_keep_hierarchy?

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Contributor
Contributor
7,182 Views
Registered: ‎10-21-2012

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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Unfortunately, I am locked into the version of the tools because of company restrictions, so I can't upgrade. I also tried adding -ignore_keep_hierachy and I still end up with errors.

 

Thanks

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Scholar austin
Scholar
9,429 Views
Registered: ‎02-27-2008

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

Jump to solution

File a webcase, and report it as a bug.

 

If you do not have access to webcase, let me know, so I may forward it.

 

We are working on a way to report bugs for anyone/everyone.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Contributor
Contributor
7,178 Views
Registered: ‎10-21-2012

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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Thanks Austin, will do.

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Xilinx Employee
Xilinx Employee
7,170 Views
Registered: ‎07-01-2008

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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Chances are this trimming problem is a design issue rather than a bug.

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Scholar austin
Scholar
7,166 Views
Registered: ‎02-27-2008

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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b,

 

That is very often the case.  But, as you know, "the customer is always right."

 

So, if we need to find their bug, for them, we do.

 

And, sometimes we find that we have a bug.

 

It does look very odd that it is an error, as trimming unused logic is usually just a warning....(trim it, and evrything is just fine).

Austin Lesea
Principal Engineer
Xilinx San Jose
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Contributor
Contributor
3,567 Views
Registered: ‎10-21-2012

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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It could definitely be possible that somewhere I did something stupid in the design, however, I am not 100% that this is a design issue because I actually have this core working in 14.2 on a Zedboard. The only difference in the projects are 3 NGCs I have to generate in coregen, and this seems to be complaining about the divider ngc. Thanks for your time and input.
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Xilinx Employee
Xilinx Employee
3,567 Views
Registered: ‎07-01-2008

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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We have always errored on undriven LUT inputs as it's not valid to use a non-existant term in an equation. Vivado does the same.

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Scholar austin
Scholar
3,556 Views
Registered: ‎02-27-2008

Re: MapLib: 979 LUT Symbol <sig> has input signal <sig> which will be trimmed

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b,

 

Interesting.  I always thought we just trimmed stuff if left unconnected.  But, it is always better to error if it appears that something SHOULD be connected, and it isn't.

 

An unconnected input is odd.  I suppose I have always had unconnected outputs (unused) in my experience.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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