UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer vjose
Observer
6,964 Views
Registered: ‎08-01-2012

Mapping Error

Jump to solution

Hi ,

 

I have an IP core from a third party . When I try to generate a bit file using this IP core , I get the following error

 

ERROR:Pack:2811 - Directed packing was unable to obey the user design
   constraints (MACRONAME=U_PCD03V_U_INT3G/U_INT3G4, RLOC=X1Y0) which requires
   the combination of the symbols listed below to be packed into a single SLICE
   component.

 

With regards

Vintu

0 Kudos
1 Solution

Accepted Solutions
Observer vjose
Observer
11,112 Views
Registered: ‎08-01-2012

Re: Mapping Error

Jump to solution

Hi ,

 

Thanks for the link .

 

I tried to clean the project again and run . No things are working fine .

 

Thanks for the help

 

With regards

Vintu

0 Kudos
4 Replies
Xilinx Employee
Xilinx Employee
6,951 Views
Registered: ‎04-16-2012

Re: Mapping Error

Jump to solution

Hi,

 

Do you have any RLOC constraints in the design?

try running map with "-ir all" switch.

 

Thanks.

--------------------------------------------------------------------------------------------
Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.
0 Kudos
Xilinx Employee
Xilinx Employee
6,939 Views
Registered: ‎07-01-2008

Re: Mapping Error

Jump to solution

You didn't provide the entire message so all we know is that RLOC constraints are causing the problem. The message also describes the nature of the conflict and lists the instances involved.

 

Are you instantiating the core more than once? If so, the provider may have used the U_SET grouping attribute for the macro which would cause the multiple instantiations to overlap.

 

http://www.xilinx.com/support/answers/29711.htm

0 Kudos
Observer vjose
Observer
11,113 Views
Registered: ‎08-01-2012

Re: Mapping Error

Jump to solution

Hi ,

 

Thanks for the link .

 

I tried to clean the project again and run . No things are working fine .

 

Thanks for the help

 

With regards

Vintu

0 Kudos
Moderator
Moderator
6,900 Views
Registered: ‎06-05-2013

Re: Mapping Error

Jump to solution

Is it working or not working?

Please indicate properly.

Thanks

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos