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Explorer
Explorer
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Registered: ‎07-29-2009

Match types between connected pins

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when I get a warning like this:

WARNING: [BD 41-1731] Type mismatch between connected pins: /verandfreqcount_0/onepps(undef) and /onepps(clk)

 

What's the best way to set the type on verandfreqcount_0/onepps?
Example with both the command line and the createandpackage IP tool?

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Explorer
Explorer
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Registered: ‎07-29-2009

Re: Match types between connected pins

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This is the ipx version of it on the command line, but I was wondering if it's possible after the fact or if there were others.

 

ipx::infer_bus_interface onepps xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface highspeedclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

 

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Moderator
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Registered: ‎11-09-2015

Re: Match types between connected pins

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Hi @petersk,

 

The best way is when you package the IP. In the port definition, just change the type to clk.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Explorer
Explorer
8,386 Views
Registered: ‎07-29-2009

Re: Match types between connected pins

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This is the ipx version of it on the command line, but I was wondering if it's possible after the fact or if there were others.

 

ipx::infer_bus_interface onepps xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface highspeedclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

 

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Visitor
Visitor
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Registered: ‎03-22-2018

Re: Match types between connected pins

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Where would you change the port definition to clk?

ports.png

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Visitor
Visitor
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Registered: ‎03-22-2018

Re: Match types between connected pins

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Sorry, it was already in this thread and I missed it. Simply right click on the port and "Auto infer"...
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