cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
6,182 Views
Registered: ‎07-29-2009

Match types between connected pins

Jump to solution

when I get a warning like this:

WARNING: [BD 41-1731] Type mismatch between connected pins: /verandfreqcount_0/onepps(undef) and /onepps(clk)

 

What's the best way to set the type on verandfreqcount_0/onepps?
Example with both the command line and the createandpackage IP tool?

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Explorer
Explorer
8,870 Views
Registered: ‎07-29-2009

This is the ipx version of it on the command line, but I was wondering if it's possible after the fact or if there were others.

 

ipx::infer_bus_interface onepps xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface highspeedclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

 

View solution in original post

0 Kudos
4 Replies
Highlighted
Moderator
Moderator
6,169 Views
Registered: ‎11-09-2015

Hi @petersk,

 

The best way is when you package the IP. In the port definition, just change the type to clk.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Explorer
Explorer
8,871 Views
Registered: ‎07-29-2009

This is the ipx version of it on the command line, but I was wondering if it's possible after the fact or if there were others.

 

ipx::infer_bus_interface onepps xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface highspeedclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

 

View solution in original post

0 Kudos
Highlighted
Visitor
Visitor
4,278 Views
Registered: ‎03-22-2018

Where would you change the port definition to clk?

ports.png

Tags (1)
0 Kudos
Highlighted
Visitor
Visitor
4,266 Views
Registered: ‎03-22-2018
Sorry, it was already in this thread and I missed it. Simply right click on the port and "Auto infer"...
0 Kudos