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Observer sachinb_apt1
Observer
287 Views
Registered: ‎01-03-2018

Max Fanout ignored by Vivado

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Hi,

 I am using vivado 2017.3 for VU9P device as my target. For a critical timing path, i applied a max fanout constraint (of 21) to one of the nets.

However, i see that the fanout on that net is high as it was before applying the constraint. I see the properties section for the net and i noticed that the MAX FANOUT attribute is still what i  set in the Max FO constraint (i.e 21), however, Flat pin count number number for that net is 253.

I dont understand why the flat pin count is so high compared to the max fanout constraint. I expected it to be 22 (fanout of 21 plus 1 driver pin).

See the picture attached.

max fanout issue.png
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Observer sachinb_apt1
Observer
207 Views
Registered: ‎01-03-2018

Re: Max Fanout ignored by Vivado

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I think i got the problem. In my constraint, i had the filter REF_NAME =~ "*FD*". Probably that was the reason. Since i removed the fanout has come down (but not to the level of constarint) but atleast the get_cells is not ignored during synthesis now.

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Observer sachinb_apt1
Observer
285 Views
Registered: ‎01-03-2018

Re: Max Fanout ignored by Vivado

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The driver of the net is a FF. So i dont see any reason why tool couldnt have replicated it and reduced the fan out on the net.
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250 Views
Registered: ‎01-22-2015

Re: Max Fanout ignored by Vivado

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@sachinb_apt1

Implementation (placer) appears to have difficulty with MAX_FANOUT.  As shown in <this> post, a CR was filed in July 2018 by syedz to correct this.

Cheers,
Mark

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Observer sachinb_apt1
Observer
246 Views
Registered: ‎01-03-2018

Re: Max Fanout ignored by Vivado

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The problem is with tools handling of max_fanout constraint right from begining

So when i give the max_fanout using get_nets -of_objects [get_pins -of_objects [get_cells <my_design_hierarchial-path>/* -filter {REF_NAME =~ "*FD*"}] -filter {DIRECTION == OUT}]] , in constraints file during synthesis, the synthesis tool ignores the constraint saying that it could not find the cells (get_cells fails). The get_cells however works in postsynth.dcp where it returns the cells.

Since Synthesis fails with get_cells, i put them in seperated xdc file and use it in implementation phase (used_in = implementation). So it accepts the max_fanout but doesnt apply it. The snapshot i attached was from post_opt dcp. Despite MAX_FANOUT on net clearly visible as 21, the flat pin count is 253.

So basically i am stuck... Synthesis cannot find the cells and post synthesis the constraint isnt applied.

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Xilinx Employee
Xilinx Employee
212 Views
Registered: ‎07-16-2008

Re: Max Fanout ignored by Vivado

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MAX_FANOUT affects synthesis step.

If the specified cells are within OOC IP, it's not seen by the tool in top level synthesis as the IP is treated as black box. When you open the synthesized design, the IP netlist is linked and the cell is returned.

 

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Observer sachinb_apt1
Observer
208 Views
Registered: ‎01-03-2018

Re: Max Fanout ignored by Vivado

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I think i got the problem. In my constraint, i had the filter REF_NAME =~ "*FD*". Probably that was the reason. Since i removed the fanout has come down (but not to the level of constarint) but atleast the get_cells is not ignored during synthesis now.

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Moderator
Moderator
123 Views
Registered: ‎01-16-2013

Re: Max Fanout ignored by Vivado

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@sachinb_apt1

 

If you have no futher query and if your query is resolved, Can you please close this thread by marking the helpful post as "Accept as Solution"

 

--Syed

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