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Visitor
Visitor
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Registered: ‎06-11-2016

Maximum speed of LVCMOS I/O

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Hello,

 

    I have a question that I need your help: What is the maximum speed of LVCMOS I/O of FPGA Spartan-3? Can you list the speed of each LVCMOS33, 25, 18, 15, 12?

 

Thank you so much,

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Xilinx Employee
Xilinx Employee
10,737 Views
Registered: ‎08-01-2012
  • The IO standards in Xilinx FPGA designed as per JDEC standards. So all standard specification applicable for Spartan-3 also.
  • The maximum speed is mainly depended upon IO type, and also end user board physics..etc. So we will not specify maximum speed in document because of end user board/PCB design dependencies. This was specified in http://www.xilinx.com/support/answers/12866.htm  and concepts are applicable for all FPGA devices also
  • The work around for customer on this issue is Signal Integrity (SI) simulations by using IBIS model and board transmission line models.
  • XILINX provided IBIS models for this purpose. By using IBIS simulations as per his board design customer can expect speed and other SI result even before the design. You can download Spartan-3 IBIS models from the below link:             http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-models/mature.html
  • Information in below link documents and training material helpful to understand and do SI simulations

         http://www.xilinx.com/products/technology/signal-integrity.html

________________________________________________

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Highlighted
Xilinx Employee
Xilinx Employee
10,738 Views
Registered: ‎08-01-2012
  • The IO standards in Xilinx FPGA designed as per JDEC standards. So all standard specification applicable for Spartan-3 also.
  • The maximum speed is mainly depended upon IO type, and also end user board physics..etc. So we will not specify maximum speed in document because of end user board/PCB design dependencies. This was specified in http://www.xilinx.com/support/answers/12866.htm  and concepts are applicable for all FPGA devices also
  • The work around for customer on this issue is Signal Integrity (SI) simulations by using IBIS model and board transmission line models.
  • XILINX provided IBIS models for this purpose. By using IBIS simulations as per his board design customer can expect speed and other SI result even before the design. You can download Spartan-3 IBIS models from the below link:             http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-models/mature.html
  • Information in below link documents and training material helpful to understand and do SI simulations

         http://www.xilinx.com/products/technology/signal-integrity.html

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

View solution in original post

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