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Observer fasih.ahmed
Observer
325 Views
Registered: ‎07-15-2019

Memory Interface

Dear All,

I want to know the memory interface process of FPGA's. For example, if I 
have a hardware model project and want to transfer that information to 
the software developer, If I am working on the SDx(software 
development)  how would I know which particular file contain this 
information.

Actually, I am working to create the memory interface for FPGA 
communication-based on the model pushed into the FPGA.

I look forward to your favorable response and thank you in advance for 
your time and consideration.

BR,

Ahmed

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4 Replies
Scholar dgisselq
Scholar
295 Views
Registered: ‎05-21-2015

Re: Memory Interface

@fasih.ahmed,

I've stared at this question now several times, and ... I'll admit, I haven't answered yet because I'm not really certain what you are asking.

  1. Xilinx FPGAs can interact with lots of different memories.  Each memory standard tends to be subtly different.  From this standpoint, there is no one memory model which everything adheres to.
  2. Internal to the FPGA, Xilinx (and perhaps ARM?) have been promoting a communications protocol called AXI.  Both Zynq and MicroBlaze processors will communicate with the rest of the design using AXI interfaces.  Indeed, this is the recommended interface when connecting components together.  (It's not an easy interface to get right ... but we can save that for another topic.)

Are either of these what you are asking?

Dan

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Observer fasih.ahmed
Observer
284 Views
Registered: ‎07-15-2019

Re: Memory Interface

@dgisselq Thank you so much for your reply, I mean to say that from where I can get information about the things like (min address, max address, base address & range). I can assign this information of any model by myself which helps to improve the technical readiness of the already existing FPGA prototype.

I hope you understand my question :)

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Scholar dgisselq
Scholar
274 Views
Registered: ‎05-21-2015

Re: Memory Interface

Wouldn't those parameters be design dependent?  They'd be parameters of the interconnect, so you should be able to click on that, or open it up (depending on the type of interconnect you are using) and see what choices have been made.  Since they are design dependent though, they can easily change as the design is reconfigured.  That's why Vivado exports them to a linker script that software can then use for this purpose.

While I'm not so familiar with the linker scripts Vivado generates, I do know that GNU's linker script format allows you to include symbols in the linker script that can then be used by software to know where things have been placed in the address space.

Dan

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Observer fasih.ahmed
Observer
188 Views
Registered: ‎07-15-2019

Re: Memory Interface

Hey Dan,

sds_lib.h library can help me I guess ?. Do you know any idea about this library and another library which also deals with the memory interface for FPGA communication?

BR,

Thanks in advance

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