08-18-2019 08:07 AM
I want to know the memory interface process of FPGA's. For example, if I
have a hardware model project and want to transfer that information to
the software developer, If I am working on the SDx(software
development) how would I know which particular file contain this
Actually, I am working to create the memory interface for FPGA
communication-based on the model pushed into the FPGA.
I look forward to your favorable response and thank you in advance for
your time and consideration.
08-18-2019 06:14 PM
I've stared at this question now several times, and ... I'll admit, I haven't answered yet because I'm not really certain what you are asking.
Are either of these what you are asking?
08-18-2019 11:03 PM
@dgisselq Thank you so much for your reply, I mean to say that from where I can get information about the things like (min address, max address, base address & range). I can assign this information of any model by myself which helps to improve the technical readiness of the already existing FPGA prototype.
I hope you understand my question :)
08-19-2019 04:49 AM
Wouldn't those parameters be design dependent? They'd be parameters of the interconnect, so you should be able to click on that, or open it up (depending on the type of interconnect you are using) and see what choices have been made. Since they are design dependent though, they can easily change as the design is reconfigured. That's why Vivado exports them to a linker script that software can then use for this purpose.
While I'm not so familiar with the linker scripts Vivado generates, I do know that GNU's linker script format allows you to include symbols in the linker script that can then be used by software to know where things have been placed in the address space.
09-23-2019 06:53 AM
sds_lib.h library can help me I guess ?. Do you know any idea about this library and another library which also deals with the memory interface for FPGA communication?
Thanks in advance