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Visitor
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Registered: ‎04-18-2018

Memory leak during implementation with Vivado 18.1

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Dear All,

 

I have a Virtex-7 design that builds in Vivado 16.4 and 17.X, but during implmentation in 18.1 there seems to be a memory leak.  Peak memory usage is normally ~5GB, but with 18.1 the memory requirements keep increasing until the machine freezes.  I am using Centos-7 with 32GB of RAM.   I am not entirely sure how to debug this or whether it is even possible as a user.  I haven't found anything significant in the logs yet.  Any advice would be most welcome. 

 

Greg

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Moderator
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Registered: ‎02-07-2008

Re: Memory leak during implementation with Vivado 18.1

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@ilesgm, thanks for assistance. Issued reproduced with CR filed.

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Registered: ‎02-07-2008

Re: Memory leak during implementation with Vivado 18.1

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@ilesgm, can you attached the implementation runme.log file? 

 

Are you able to submit a post-synthesis DCP that would enabled us to investigate this issue internally?

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Re: Memory leak during implementation with Vivado 18.1

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Thanks.  Logfile attached.  I'll work out how to submit a post-synthesis DCP later.  The last thing the log file mentions is overlapping p-blocks, but it hasn't been a problem in the past and it is just one of many warnings - but perhaps times have changed!

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Registered: ‎02-07-2008

Re: Memory leak during implementation with Vivado 18.1

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@ilesgm, thanks for assistance. Issued reproduced with CR filed.

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